SDAS083B - APRIL 1982 - REVISED DECEMBER 1994
description
These octal transparent D-type latches feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.
While the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the logic levels set up at the D inputs.
A buffered output-enable (
) input can be used to place the eight outputs in either
a normal logic state (high or low) or a high-impedance state. In the
high-impedance state, the outputs neither load nor drive the bus
lines significantly. The high-impedance state and the increased drive
provide the capability to drive bus lines without interface or pullup
components.
does not affect
internal operations of the latches. Old data can be retained or new
data can be entered while the outputs are off.
The SN54ALS373 and SN54AS373 are characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ALS373A and SN74AS373 are characterized for operation from 0°C to 70°C.