)
input does not affect internal operations of the flip-flops.
Previously stored data can be retained or new data can be entered
while the outputs are in the high-impedance state.SDAS109D - APRIL 1989 - REVISED JANUARY 1995
This 8-bit flip-flop features 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. It is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.
The eight flip-flops of the SN74AS4374B are edge-triggered D-type flip-flops. On the second positive transition of the clock (CLK) input, the Q outputs are set to the logic levels set up at the data (D) inputs.
The output-enable ()
input does not affect internal operations of the flip-flops.
Previously stored data can be retained or new data can be entered
while the outputs are in the high-impedance state.
The SN74AS4374B is characterized for operation from 0°C to 70°C.