) output indicates whether or not
an error in the B data has occurred. The output-enable (
, 
) inputs can be used to disable the device so that the
buses are effectively isolated.SDAS118C - FEBRUARY 1987 - REVISED JANUARY 1995
The SN74ALS29854 is an 8-bit to 9-bit parity transceiver designed
for two-way communication between data buses. When data is
transmitted from the A bus to the B bus, a parity bit is generated.
When data is transmitted from the B bus to the A bus with its
corresponding parity bit, the parity-error () output indicates whether or not
an error in the B data has occurred. The output-enable (, ) inputs can be used to disable the device so that the
buses are effectively isolated.
A 9-bit parity generator/checker generates a parity-odd (PARITY)
output and monitors the parity of the I/O ports with an
open-collector flag. can
be either passed, sampled, stored, or cleared from the latch using
the latch-enable (
) and clear
(
) control
inputs. When both OEA\ and OEB\ are low, data is transferred from the
A bus to the B bus and inverted parity is generated. Inverted parity
is a forced error condition that gives the designer more system
diagnostic capability.
The SN74ALS29854 is characterized for operation from 0°C to 70°C.