SN74ALS29833
8-BIT TO 9-BIT PARITY BUS TRANSCEIVER

SDAS119D - FEBRUARY 1987 - REVISED JANUARY 1995

features

• Functionally Similar to AMD's AM29833
• High-Speed Bus Transceiver With Parity Generator/Checker
• Parity-Error Flag With Open-Collector Outputs
• Register for Storing the Parity-Error Flag
• Package Options Include Plastic Small-Outline (DW) Packages and Standard Plastic (NT) 300-mil DIPs

description

The SN74ALS29833 is an 8-bit to 9-bit parity transceiver designed for two-way communication between data buses. When data is transmitted from the A bus to the B bus, a parity bit is generated. When data is transmitted from the B bus to the A bus with its corresponding parity bit, the parity-error () output indicates whether or not an error in the B data has occurred. The output-enable (OEA\, OEB\) inputs can be used to disable the device so that the buses are effectively isolated.

A 9-bit parity generator/checker generates a parity-odd (PARITY) output and monitors the parity of the I/O ports with an open-collector flag. is clocked into the register on the rising edge of the clock (CLK) input. The error-flag register is cleared with a low pulse on the clear () input. When both and are low, data is transferred from the A bus to the B bus and inverted parity is generated. Inverted parity is a forced error condition that gives the designer more system diagnostic capability.

The SN74ALS29833 is characterized for operation from 0°C to 70°C.