SN74AS195
4-BIT BIDIRECTIONAL UNIVERSAL SHIFT REGISTER

SDAS138B - DECEMBER 1983 - REVISED JANUARY 1995

features

• Parallel-to-Serial, Serial-to-Parallel Conversions
• Parallel Synchronous Loading
• J and K\ Inputs to First Stage
• Right Shift Only With Complementary Outputs on Last Stage
• Direct Overriding Clear
• Package Options Include Plastic Small-Outline (D) Packages and Standard Plastic (N) 300-mil DIPs

description

This 4-bit bidirectional universal shift register features parallel (A, B, C, D) inputs, parallel (Q_A, Q_B, Q_C, Q_D, Q\_D) outputs, J-K\ serial (J, K\) inputs, shift/load control (SH/) input, and a direct overriding clear (). The registers have two modes of operation:

• Parallel (broadside) load
• Shift (in the direction Q_A toward Q_D)

Parallel loading is accomplished by applying the four bits of data and taking SH/ low. The data is loaded into the associated flip-flops and appears at the outputs after the positive transition of the clock (CLK) input. During loading, serial data flow is inhibited.

Shifting is accomplished synchronously when SH/ is high. Serial data for this mode is entered at the J-K\ inputs. These inputs permit the first stage to perform as a J-K\, D-, or T-type flip-flop as shown in the function table.

The SN74AS195 is characterized for operation from 0°C to 70°C.