SDAS146B - JANUARY 1986 - REVISED JANUARY 1995
These 9-bit flip-flops feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. They are particularly suitable for implementing wider buffer registers, I/O ports, bidirectional bus drivers, parity bus interfacing, and working registers.
With the clock-enable (
)
input low, the nine D-type edge-triggered flip-flops enter data on
the low-to-high transitions of the clock (CLK) input. Taking high disables the clock buffer,
latching the outputs. The ´ALS29823 have noninverting data (D)
inputs. Taking the clear (
)
input low causes the nine Q outputs to go low independently of the
clock.
A buffered output-enable (
) input places the nine outputs in either a normal logic
state (high or low logic levels) or a high-impedance state. The
outputs also are in the high-impedance state during power-up and
power-down conditions. The outputs remain in the high-impedance state
while the device is powered down. In the high-impedance state, the
outputs neither load nor drive the bus lines significantly. The
high-impedance state and increased drive provide the capability to
drive bus lines without interface or pullup components.
does not affect
the internal operation of the flip-flops. Old data can be retained or
new data can be entered while the outputs are in the high-impedance
state.
The SN54ALS29823 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ALS29823 is characterized for operation from 0°C to 70°C.