SN74ALS2238
32 × 9 × 2 ASYNCHRONOUS BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY

SDAS182 - APRIL 1990

features

• Independent Asychronous Inputs and Outputs
• Bidirectional
• 32 Words by 9 Bits
• Programmable Depth
• Data Rates from 0 to 40 MHz
• Fall-Through Time...22 ns Typ
• 3-State Outputs

  IMPACT-X is a trademark of Texas Instruments Incorporated.

description

This 576-bit memory uses advanced low-power Schottky IMPACT-X^TM technology and features high speed and fast fall-through times. It consists of two FIFOs organized as 32 words by 9 bits each.

A FIFO memory is a storage device that allows data to be written into and read from its array at independent data rates. These FIFOs are designed to process data at rates from 0 to 40 MHz in a bit-parallel format, word by word.

The SN74ALS2238 consists of bus-transceiver circuits, two 32 × 9 FIFOs, and control circuitry arranged for multiplexed transmission of data directly from the data bus or from the internal FIFO memories. Enables GAB and GBA are provided to control the transceiver functions. The SAB and SBA control pins are provided to select whether real-time or stored data is transferred. The circuitry used for select control eliminates the typical decoding glitch that occurs in a multiplexer during the transition between stored and real-time data. A low level selects real-time data and a high selects stored data. Eight fundamental bus-management functions can be performed as shown in Figure 1.

Data on the A or B data bus, or both, is written into the FIFOs on a low-to-high transition at the load clock (LDCKA or LDCKB) input and is read out on a low-to-high transition at the unload clock (UNCKA or UNCKB) input. The memory is full when the number of words clocked in exceeds, by the defined depth, the number of words clocked out.

When the memory is full, LDCK signals have no effect on the data residing in memory. When the memory is empty, UNCK signals have no effect.

Status of the FIFO memories is monitored by the,,, and output flags. The and are definable full flags. A high-to-low transition on stores the binary value of A0 through A4 into a register for use as the value of X. A high-to-low transition on stores the binary value of B0 through B4 into a register for use as the value of Y. In this way, the depth of either FIFO can be defined to be one to 32 words deep. The value of X and Y must be defined after power up or the stored value of X and Y will be ambiguous. The and outputs are low when their corresponding memories are full and high when the memories are not full.

The and outputs are low when their corresponding memories are empty and high when they are not empty. The status flag outputs are always active.

A low-level pulse on the or inputs resets the control pointers on FIFO A or FIFO B and also sets low and high or low and high. The outputs are not reset to any specific logic levels. With at a low level, a low-level pulse on sets FIFO A to a depth of 32 - X, where X is the value stored above. With at a high level, a low level pulse on sets FIFO A to a depth of 32 words. The depth of FIFO B is set in a similar manner. The first low-to-high transition on LDCKA or LDCKB, either after a reset pulse or from an empty condition, will cause or to go high and the data to appear on the Q outputs. It is important to note that the first word does not have to be unloaded. Cascading is easily accomplished in the word-width direction, but is not possible in the word-depth direction.

The SN74ALS2238 is characterized for operation from 0°C to 70°C.