SN54ALS114A, SN74ALS114A
DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS
WITH PRESET,COMMON CLEAR,AND COMMON CLOCK

SDAS201 - D2661, DECEMBER 1982 - REVISED MAY 1986

features

• Fully Buffered to Offer Maximum isolation from External Disturbance
• Package Options include Plastic Small Outline Packages, Ceramic Chip Carriers, and Standard Plastic and Ceramic 300-mil DIPs
• Typical Maximum Clock Frequency 30 MHz
• Typical Power Dissipation per Flip-Flop 6 mW
• Dependable Texas Instruments Quality and Reliability

description

These devices contain two independent J-K negative-edge-triggered flip-flops. A low level at the Preset or Clear inputs sets or resets the outputs regardless of the levels of the other inputs. When Preset and Clear are inactive (high), data at the J and K inputs meeting the setup time requirements are transferred to the outputs on the negative-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the fall time of the clock pulse. Following the hold time interval, data at the J and K inputs may be changed without affecting the levels at the outputs. These versatile flip-flops can perform as toggle flip-flops by tying J and K high.

The SN54ALS114A is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ALS114A is characterized for operation from 0°C to 70°C.