mode-control (S0, S1) inputs, and a direct overriding clear (
) line. The registers have four
distinct modes of operation:SDAS212A - DECEMBER 1983 - REVISED DECEMBER 1994
These 4-bit bidirectional universal shift registers feature
parallel outputs, right-shift and left-shift serial (SR SER, SL SER)
inputs, operating-
mode-control (S0, S1) inputs, and a direct overriding clear () line. The registers have four
distinct modes of operation:
Parallel synchronous loading is accomplished by applying the four bits of data and taking both S0 and S1 high. The data is loaded into the associated flip-flops and appears at the outputs after the positive transition of the clock (CLK) input. During loading, serial data flow is inhibited.
Shift right is accomplished synchronously with the rising edge of the clock pulse when S0 is high and S1 is low. Serial data for this mode is entered at the shift-right data input. When S0 is low and S1 is high, data shifts left synchronously and new data is entered at the shift-left serial inputs. Clocking of the flip-flop is inhibited when both mode-control inputs are low.
The SN54AS194 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74AS194 is characterized for operation from 0°C to 70°C.
H = high level (steady state); L = low level (steady state); X = irrelevant (any input, including transitions); = transition from low to high level; a, b, c, d = the level of steady-state input at inputs A, B, C, or D, respectively; QA0, QB0, QC0, QD0 = the level of QA, QB, QC, or QD, respectively, before the indicated steady-state input conditions were established; QAn, QBn, QCn, QDn = the level of QA, QB, QC, respectively, before the most recent transition of the clock.