) input is low.
A high at inhibits
counting. The direction of the count is determined by the level of
the down/up (D/U\) input. When D/U\ is low, the counter counts up,
and when D/U\ is high, it counts down.SDFS026B - D3690, JULY 1990 - REVISED OCTOBER 1993
The SN74F190A is a synchronous, 4-bit decade reversible up/down counter. Synchronous counting operation is provided by having all flip-flops clocked simultaneously so that the outputs change coincident with each other when so instructed by the steering logic. This mode of operation eliminates the output counting spikes normally associated with asynchronous (ripple-clock) counters.
The outputs of the four flip-flops are triggered on a
low-to-high-level transition of the clock (CLK) input if the enable
() input is low.
A high at inhibits
counting. The direction of the count is determined by the level of
the down/up (D/U\) input. When D/U\ is low, the counter counts up,
and when D/U\ is high, it counts down.
This counter features a fully independent clock circuit. Changes
at the control ( and D/U\)
inputs that modify the operating mode have no effect on the contents
of the counter until clocking occurs. The function of the counter is
dictated solely by the condition meeting the stable setup and hold
times. This counter is fully programmable; that is, it may be preset
to any number between 0 and 9 by placing a low on the load input and
entering the desired data at the data inputs. The output changes to
agree with the data inputs independent of the level of the clock
input. This feature allows the counter to be used as a modulo-N
divider by simply modifying the count length with the preset inputs.
Two outputs have been made available to perform the cascading
function: ripple clock and maximum/minimum count. The latter output
produces a high-level output pulse with a duration approximately
equal to one complete cycle of the clock while the count is minimum
(0) counting down or maximum (9) counting up. The ripple-clock (
) output produces a low-level
output pulse under those same conditions, but only while the clock
input is low. The counter can easily be cascaded by feeding the
ripple-clock output to the enable input of the succeeding counter if
parallel clocking is used or to the clock input if parallel enabling
is used. The maximum/minimum count (MAX/MIN) output can be used to
accomplish look-ahead for high speed operation.
The SN74F190A is characterized for operation from 0°C to 70°C.