SDFS032A - D3213, JANUARY 1989 - REVISED OCTOBER 1993
The ´F166A parallel-in or serial-in, serial-out registers
feature gated clock (CLK INH and CLK) inputs and an overriding clear
(
) input. The
parallel-in or serial-in modes are established by the shift/load
(SH/
) input. When
high, this input enables the serial data input and couples the eight
flip-flops for serial shifting with each clock pulse. When low, the
parallel (broadside) data inputs are enabled, and synchronous loading
occurs on the next clock pulse. During parallel loading, serial data
flow is inhibited.
Clocking is accomplished on the low-to-high-level edge of the
clock pulse through a two-input positive OR gate, permitting one
input to be used as a clock-enable or clock-inhibit function. Holding
either of the clock inputs high inhibits clocking; holding either low
enables the other clock input. This allows the system clock to be
free-running, and the register can be stopped on command with the
other clock input. The clock inhibit input should be changed to the
high level only when the clock input is high. The direct clear () overrides all other inputs,
including the clock, and resets all flip-flops to zero.
The SN54F166A is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74F166A is characterized for operation from 0°C to 70°C.