SDLS213 - DECEMBER 1983 - REVISED MAY 1994
The ´221 and ´LS221 are monolithic dual multivibrators
with performance characteristics virtually identical to those of the
´121. Each multivibrator features a negative-transition-
triggered input and a positive-transition-triggered input either of
which can be used as an inhibit input.
Pulse triggering occurs at a particular voltage level and is not directly related to the transition time of the input pulse. Schmitt-trigger input circuitry (TTL hysteresis) for B input allows jitter-free triggering from inputs with transition rates as slow as 1 V/s, providing the circuit with excellent noise immunity of typically 1.2 V. A high immunity to VCC noise of typically 1.5 V is also provided by internal latching circuitry.
Once fired, the outputs are independent of further transitions of
the A and B inputs and are a function of the timing components, or
the output pulses can be terminated by the overriding clear. Input
pulses can be of any duration relative to the output pulse. Output
pulse length can be varied from 35 ns to the maximums shown in the
above table by choosing appropriate timing components. With
Rext = 2 k
and
Cext = 0, an output pulse of typically 30 ns is achieved
which can be used as a dc-triggered reset signal. Output rise and
fall times are TTL compatible and independent of pulse length.
Typical triggering and clearing sequences are illustrated as a part
of the switching characteristics waveforms.
Pulse-width stability is achieved through internal compensation and is virtually independent of VCC and temperature. In most applications, pulse stability is only limited by the accuracy of external timing components.
Jitter-free operation is maintained over the full temperature and
VCC ranges for more than six decades of timing capacitance
(10 pF to 10 
F) and more
than one decade of timing resistance (2 k to 30 k for the SN54221, 2 k to 40 k for the SN74221, 2 k to 70 k for the SN54LS221, and 2 k to 100 k for the SN74LS221). Throughout
these ranges, pulse width is defined by the relationship:
tw(out) = CextRext In2 = 0.7
CextRext. In circuits where pulse cutoff is not
critical, timing capacitance up to 1000 uF and timing resistance as
low as 1.4 k can be used.
Also, the range of jitter-free output pulse widths is extended if
VCC is held to 5 V and free-air temperature is 25°C.
Duty cycles as high as 90% are achieved when using maximum
recommended RT. Higher duty cycles are available if a
certain amount of pulse-width jitter is allowed.
The variance in output pulse width from device to device is typically less than ±0.5% for given external timing components. An example of this distribution for the ´221 is shown in Figure 2. Variations in output pulse width versus supply voltage and temperature for the ´221 are shown in Figures 3 and 4, respectively.
Pin assignments for these devices are identical to those of the SN54123/SN74123 or SN54LS123/SN74LS123 so that the ´221 or ´LS221 can be substituted for those products in systems not using the retrigger by merely changing the value of Rext and/or Cext; however, the polarity of the capacitor will have to be changed.
The SN54221 and SN54LS221 are characterized for operation over the full military temperature range of -55°C to 125°C. The SN74221 and SN74LS221 are characterized for operation from 0°C to 70°C.