SDNS001B - SEPTEMBER 1992 - REVISED DECEMBER 1994
The TNETA1555 device recovers an embedded clock signal from a 155.52-Mbit/s STS-3/STM-1 nonreturn-to-zero (NRZ) data stream using a frequency/phase-locked loop. The device accepts PECL (ECL signals referenced to 5 V instead of GND) input-voltage levels. The recovered clock and data outputs are PECL compatible. The serial data input and recovered clock and data outputs are differential to provide maximum noise immunity.
The input disable (INDIS) disconnects the incoming serial data stream from the clock-recovery circuitry. When the INDIS input is high, the data output is forced low and the clock-recovery circuitry maintains the output frequency present at the time the input was disabled for a specific amount of time. This time is dependent upon the value of the capacitor in the loop filter.
A PECL-to-ECL converter is included in the device for those applications where an interface between the two different voltage levels is required. An example of such an application is an optical transmitter that requires ECL input voltage levels and a parallel-to-serial converter with pseudo-ECL-level outputs.
The TNETA1555 requires only a positive 5-V supply (5 V ± 5 %) for operation. The device is characterized for operation over a temperature range of -40°C to 85°C.