SDNS010C - JANUARY 1994 - REVISED OCTOBER 1995
The TNETA1560 is an asynchronous transfer mode (ATM) segmentation and reassembly (SAR) device with an SBus interface. This device incorporates ATM adaptation-layer (AAL) processing, ATM SAR processing for full-duplex operation up to the STS-3c rate of 155.52 Mbit/s, and the controls for the register interface on the physical (PHY) layer. The device provides a packet interface that is managed by descriptor rings, making the 53-byte ATM-framing format transparent to the user. The device passes the payload of 48 bytes, constituting the payload of each cell, across the SBus-host interface. All packets are segmented and reassembled in host memory and accessed by the chip via the descriptor-ring mechanism. This operation reduces the memory requirements for network-interface cards (NICs). The TNETA1560 requires no local processor on the card, which enables very compact solutions.
The applications for the TNETA1560 include NICs for client workstations and servers, embedded applications like LAN emulation, and multiprotocol systems like video servers. The TNETA1560 provides complete AAL5 encapsulation and termination in hardware. In addition, limited support is provided for AAL3/4 and a null AAL is provided to facilitate real-time data transfer. The TNETA1560 recognizes ATM-layer operation and maintenance (OAM) cells.
In the transmit direction, the TNETA1560 generates data via a special bit-rate control table that provides explicit cell-level interleaving between groups of virtual circuits (VCs). This mechanism brings a higher degree of flexibility when specifying peak rates for each group (up to 155.52 Mbit/s at a resolution greater than 32 kbit/s). The VCs within a group are serviced via a first-in, first-out (FIFO) discipline on a per-packet basis.
In the receive direction, the TNETA1560 allows multiple virtual paths (VPs) with the condition that each VC is unique. The device is primarily intended for AAL5 encapsulation and termination that is supported in hardware.
The TNETA1560 has four interfaces that include: the SBus interface with a 32-bit-wide data bus, the cell interface, a control-memory interface to access the local SRAM, and the local-bus interface to access the PHY-layer register and an EPROM. The cell interface to the PHY layer consists of an 8-bit-wide data path and associated control signals in both the transmit and receive directions. The 53-byte ATM cells pass between the ATM and PHY layers.