TNETA1570
ATM SEGMENTATION AND REASSEMBLY DEVICE
WITH INTEGRATED 64-BIT PCI-HOST INTERFACE

SDNS033B - JUNE 1995 - REVISED MAY 1996

features

• Single-Chip Segmentation and Reassembly Device (SAR) for Full-Duplex ATM-Adaptation-Layer (AAL) Processing
• Integrated 64-Bit Peripheral-Component Interface for Transferring Data and Control Information for Packet Segmentation and Packet Reassembly
• Provides Complete Encapsulation and Termination of AAL5 Packets
• Supports Both Transmit and Receive Buffer Chaining (Buffer Scatter/Gather)
• Provides for Early Segmentation of a Transmit Packet by Beginning the Segmentation Process Once a Transmit Buffer Is Available Instead of Waiting for the Entire Packet to Be Buffered
• Provides Full VPI/VCI Support and Allows for the Simultaneous Segmentation of 1023 Packets and the Simultaneous Reassembly of 30720 Packets
• Byte-Wide Cell Interface Is Full Duplex and Compliant to the ATM-Forum UTOPIA Document
• Cell Interface Can Be Programmed to Operate as Either a Physical (PHY)-Layer Interface or as a ATM-Layer Interface
• Provides Reassembly Time-Out for an Incoming Packet
• Provides a High-Priority Mechanism for Transmitting Constant-Bit-Rate Traffic
• Provides Support for Transparent/Null AAL

description

The TNETA1570 is an asynchronous transfer mode (ATM) segmentation and reassembly (SAR) device with a 64-bit peripheral component interconnect (PCI)-bus interface. This device incorporates ATM adaptation-layer (AAL) processing, ATM SAR processing for full-duplex operation up to STS-3c rate of 155.52 Mbit/s, and the controls for the register interface on the PHY layer. The device provides complete encapsulation and termination of AAL5 packets in hardware.

The TNETA1570 supports high-speed networking applications utilizing ATM protocols as either a backbone/backplane or desktop technology. Features include: high level of VPI/VCI support, high-priority segmentation option for constant-bit-rate traffic, early buffer segmentation, buffer scatter/gather capability, and 32-/64-bit PCI-bus support.

The device contains an integrated 32-/64-bit PCI interface for transferring data and control information. The segmentation and reassembly processes use host memory for storing packets that are transmitted or received. No local-packet memory is required. The device is capable of segmenting up to 1023 packets simultaneously and reassembling 30720 packets simultaneously. The device supports the full range of VPI/VCI values for both transmit and receive operations.

The TNETA1570 also supports two methods of transporting a transparent/null AAL used for transferring proprietary information. In addition, the device recognizes ATM-layer OAM cells and provides a mechanism for handling these cells. The device contains a full-duplex, byte-wide cell interface compliant to the ATM-Forum UTOPIA specification. The cell interface can be programmed to operate as either a PHY-layer interface or a ATM-layer interface.

The integrated PCI-host interface operates as either a 32-bit or 64-bit interface for DMA operations. The device operates as a 64-bit interface if the target device can accept 64-bit transfers; otherwise, it operates as a 32-bit interface. The PCI-host interface provides both master and slave capability and operates at a frequency up to 33 MHz. The PCI-host interface is functionally compliant to the PCI-local-bus specification revision 2.0. The TNETA1570 operation is explained in detail in the Principles of Operation section.