TNETA1575
ATM SEGMENTATION AND REASSEMBLY DEVICE
WITH PCI-HOST AND COPROCESSOR INTERFACES

SDNS040A - MAY 1996 - REVISED JUNE 1996

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

features

• Supports Segmentation and Reassembly of AAL5 Packets in Accordance With ITU-T Specifications I.361 and I.363 (11/93 Update)
• Integrated 32-Bit PCI Bus 2.1 (06/95) Interface for Transferring Packet Data to and From Host Memory
• Provides Simultaneous Segmentation of up to 2048 Packets
• Provides Simultaneous Reassembly of up to 2048 Packets
• Provides Full VPI/VCI Support (12 VPI Bits and 16 VCI Bits) for Transmit and Receive Operations
• Supports Constant-Bit-Rate (CBR) Traffic via High-Priority Mechanism or Local Static Scheduler Table
• Backward Compatible With the TNETA1570 in 32-Bit PCI Mode
• Provides Support for Available-Bit-Rate (ABR) Traffic via External Coprocessor Interface (COPI)
• Provides Support for VBR-nrt, VBR-rt, and UBR Traffic via External COPI
• Transmit-Channel Sleep Mode Prevents the SAR Polling Channels When No Packets Are Queued
• High-Performance Features Include Use of Sideband Signals to Reduce Polling Across the PCI Bus
• Host Accesses to the PHY-Layer Device Can Be Performed Indirectly via the TNETA1575 Local Peripheral Bus
• Local Peripheral Bus Maps the PHY Device Into the TNETA1575's PCI-Bus Address Space
• Supports Easy Access to the AAL5 Trailer Information
• Supports Buffer Scatter/Gather (Transmit and Receive Buffer Chaining)
• Optional Early Segmentation of Packets, So Segmentation Begins Once a Transmit Buffer Is Filled, Instead of Waiting for the Entire Packet to Be Available in Host Memory
• Calculates the HEC Byte for the Header of an Outgoing Cell
• Checks the HEC Byte of an Incoming Cell
• UTOPIA Level 1-Compliant Cell Interface
• Internal 32-Cell Receive FIFO
• Cell Interface Can Be Programmed to Operate as Either a Physical (PHY-Layer) Interface or as a SAR/Switch (ATM-Layer) Interface
• Provides Reassembly Time Out for Incoming Packets
• Provides an Internal Loopback Capability From Transmit to Receive
• Supports Boundary Scan Through a Five-Wire JTAG Interface in Accordance With IEEE Std 1149.1-1990 (Includes IEEE Std 1149.1a-1993)

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description

The TNETA1575 is an asynchronous transfer mode (ATM) segmentation and reassembly (SAR) device with a peripheral component interconnect (PCI)-bus interface and a coprocessor interface (COPI). The TNETA1575 continues the line of Texas Instruments (TI) ATM SAR devices directed toward the classical LAN-to-ATM translation market segment. Features have been extended to include the COPI interface, which interfaces to an external scheduler with high-performance features to eliminate polling on the PCI bus. The TNETA1575 is designed for the emerging class of high-performance enterprise networking hubs, which utilize ATM in the backplane, in addition to the traditional frame-/packet-based bus systems. Some of the features required for this application include: high level of virtual channel/virtual path support; support for isochronous services; early segmentation; and high-performance, 32-bit PCI-bus support. The feature set required by cell-switching enterprise hubs is different from the sets being offered by other SAR devices, which are directed primarily toward the adapter card market.

This data sheet provides information on the hardware specifications of the TNETA1575 device. The document contains information on the device interfaces, timing diagrams, electrical characteristics, the terminal and package information, and an overview of the device operation. All the information on the TNETA1575 data structures, configuration, and features is provided in the TNETA1575 Programmer's Reference Guide, literature number SDNU015.