SN100KT5573
OCTAL ECL-TO-TTL TRANSLATOR WITH D-TYPE
TRANSPARENT LATCHES AND 3-STATE OUTPUTS

SDZS016 - MAY 1990 - REVISED OCTOBER 1990

features

• 100K Compatible
• ECL and TTL Control Inputs
• Noninverting Outputs
• Flow-Through Architecture Optimizes PCB Layout
• Center-Pin V_CC, V_EE, and GND Configurations Minimize High-Speed Switching Noise
• Package Options Include "Small Outline" Packages and Standard Plastic 300-mil DIPs

description

This octal ECL-to-TTL translator is designed to provide efficient translation between a 100K ECL signal environment and a TTL signal environment. This device is designed specifically to improve the performance and density of ECL-to-TTL CPU/bus-oriented functions such as memory address drivers, clock drivers, and bus oriented receivers and transmitters.

The eight latches of the SN100KT5573 are transparent D-type latches. While latch enable () is low, the Q outputs follow the data (D) inputs. When is high, the Q outputs are latched at the levels that were set up at the D inputs.

A buffered output-enable input () can be used to place the eight outputs in either a normal logic state (high or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without need for interface or pullup components. Output-enable does not affect the internal operations of the latches. Old data can be retained or new data can be entered while the outputs are off.

The SN100KT5573 is characterized for operation from 0° to 85° C.