SN54ABT18245
SCAN TEST DEVICE WITH 18-BIT BUS TRANSCEIVERS

SGBS307A - AUGUST 1994 - REVISED JANUARY 1995

• Member of the Texas Instruments SCOPE^TM Family of Testability Products
• Member of the Texas Instruments Widebus^TM Family
• Compatible With the IEEE Standard 1149.1-1990 (JTAG) Test Access Port and Boundary-Scan Architecture
• SCOPE^TM Instruction Set
  • IEEE Standard 1149.1-1990 Required Instructions, CLAMP and HIGHZ
  • Parallel-Signature Analysis at Inputs
  • Pseudo-Random Pattern Generation From Outputs
  • Sample Inputs/Toggle Outputs
  • Binary Count From Outputs
  • Device Identification
  • Even-Parity Opcodes
• State-of-the-Art EPIC-IIB^TM BiCMOS Design Significantly Reduces Power Dissipation
• Packaged in 380-mil Fine-Pitch Ceramic Flat Packages Using 25-mil Center-to-Center Spacings

  SCOPE, Widebus, and EPIC-IIB are trademarks of Texas Instruments Incorporated.

   

description

The SN54ABT18245 scan test device with 18-bit bus transceivers is a member of the Texas Instruments SCOPE^TM testability integrated circuit family. This family of devices supports IEEE Standard 1149.1-1990 boundary scan to facilitate testing of complex circuit-board assemblies. Scan access to the test circuitry is accomplished via the 4-wire test access port (TAP) interface.

In the normal mode, this device contains 18-bit noninverting bus transceivers. It can be used either as two 9-bit transceivers or one 18-bit transceiver. The test circuitry can be activated by the TAP to take snapshot samples of the data appearing at the device pins or to perform a self test on the boundary-test cells. Activating the TAP in the normal mode does not affect the functional operation of the SCOPE^TM bus transceivers.

Data flow is controlled by the direction-control (DIR) and output-enable () inputs. Data transmission is allowed from the A bus to the B bus or from the B bus to the A bus depending upon the logic level at DIR. The output-enable () can be used to disable the device so that the buses are effectively isolated.

In the test mode, the normal operation of the SCOPE^TM bus transceivers is inhibited and the test circuitry is enabled to observe and control the I/O boundary of the device. When enabled, the test circuitry performs boundary-scan test operations according to the protocol described in IEEE Standard 1149.1-1990.

Four dedicated test pins observe and control the operation of the test circuitry: test data input (TDI), test data output (TDO), test mode select (TMS), and test clock (TCK). Additionally, the test circuitry performs other testing functions such as parallel-signature analysis (PSA) on data inputs and pseudo-random pattern generation (PRPG) from data outputs. All testing and scan operations are synchronized to the TAP interface.

The SN54ABT18245 is characterized for operation over the full military temperature range of -55°C to 125°C.