*************************************************************************** *************************************************************************** * Property of Texas Instruments Incorporated. Unauthorized * * reproduction and/or distribution is strictly prohibited. * * * * This product is protected under copyright law. * * Created 1997, (C) Copyright 1997, Texas Instruments Inc., * * All Rights Reserved * * * * UNLESS THERE IS A SIGNED, WRITTEN AGREEMENT TO THE * * CONTRARY, TEXAS INSTRUMENTS ("TI") IS PROVIDING THE SPICE * * MODELS "AS IS" AND WITHOUT ANY WARRANTY, EXPRESSED OR * * IMPLIED. TI assumes no liability for: * * 1) the accuracy of the SPICE models provided to your * * company; * * 2) the proper functioning of these SPICE models in your * * design or for any resulting applications; or * * 3) infringement of patents, copyrights or intellectual * * property rights resulting from your use of these * * SPICE models. * * * * TI provides SPICE Models as a service to our customers. * * You and your company shall not distribute, sell or give * * these models to anyone else without prior written * * permission from TI. * * * * TI reserves the right to make changes to our products or * * to discontinue any semiconductor product or service * * without notice, and advises our customers to obtain the * * latest version of relevant information to verify, before * * placing orders, that the information being relied on is * * current. * * * * Please be aware that your receipt and use of the SPICE * * information provided shall serve as acceptance of these * * terms and conditions. If you do not accept these terms, * * you should return or destroy the SPICE models and any * * other accompanying information immediately. * *************************************************************************** *************************************************************************** **LVTH182514 SPICE I/O Model **Advanced System Logic, Texas Instruments **************************************************************** * *NOTE: * The following files must be present to use this SPICE model: * H182514.LVT (netlist) * EPIC2BSE.LIB (Library file for process models) * EPIC2SEN.13 (Nominal process models, CMOS Level 13) * EPIC2SES.13 (Strong process models, CMOS Level 13) * EPIC2SEW.13 (Weak process models, CMOS Level 13) * EPIC2SEN.3 (Nominal process models, CMOS Level 3) * EPIC2SES.3 (Strong process models, CMOS Level 3) * EPIC2SEW.3 (Weak process models, CMOS Level 3) * PKGS.LIB (Library file for packages) * TSSOP64.PKG (Package parasitics) * READ.ME (General use, release notes, ...) * *INSTRUCTIONS: * To use this SPICE model, include the following lines in your main netlist: * . * . * . * .INCLUDE 'H182514.LVT' * And, one or more of the following (depending on I/Os to be modeled): * XLVTH182514__A 11 12 14 15 199 100 LVTH182514_APORT * XLVTH182514__B 11 12 14 15 199 100 LVTH182514_BPORT * XLVTH182514__CLK 1 2 199 100 LVTH182514_CLK * XLVTH182514__CLKENN 1 2 199 100 LVTH182514_CLKENN * XLVTH182514__LE 1 2 199 100 LVTH182514_LE * XLVTH182514__OEN 1 2 199 100 LVTH182514_OEN * XLVTH182514__TCK 1 2 199 100 LVTH182514_TCK * XLVTH182514__TDI 1 2 199 100 LVTH182514_TDI * XLVTH182514__TDO 4 5 6 199 100 LVTH182514_TDO * XLVTH182514__TMS 1 2 199 100 LVTH182514_TMS * . * . * . * * SPICE block diagram * Node 6 * | * o * ---- ---- * | \ | \ * Node 1 ____| \o____ Node 2 Node 4 ____| \o____ Node 5 * | / | / * | / | / * ---- ---- * * LVTH182514_CLK, LVTH182514_CLKENN LVTH182514_TDO * LVTH182514_LE, LVTH182514_OEN * LVTH182514_TCK, LVTH182514_TDI * LVTH182514_TMS * * * ---- * | \ * ____| \o____ Node 12 * | | / VCC * | | / /|\ * | ---- | * | | * | Node 199 * Node 11 --* Node 15 Node 100 * | | | * | o | * | ---- --- * | / | - * |____o/ |____ Node 14 * \ | * \ | * ---- * * LVTH182514_APORT, LVTH182514_BPORT * * * SPICE FUNCTION TABLE * ------------------------------------------------------------- * | NODE | | NODE | | NODE | | * |------|OPERATION|---------|OPERATION|------------|OPERATION| * | 1 2 | | 4 5 6 | | 11 12 14 15| | * |------+---------+---------+---------+------------+---------| * | L H | Input | L H L | Output | L H X H | Input | * | H L | Input | H L L | Output | H L X H | Input | * | | | X Z H | Hi-Z | H L L L | Output | * | | | | | L H H L | Output | * | | | | | Z X X H | Hi-Z | * ------------------------------------------------------------- * * Please refer to the 'READ.ME' file for general instructions for use. * * LVTH182514 SPICE I/O MODEL SUBCIRCUIT * SYSTEM PERFORMANCE PRODUCTS * ADVANCED SYSTEM LOGIC, TEXAS INSTRUMENTS * * SUBCIRCUITS: LVTH182514_APORT, LVTH182514_BPORT, LVTH182514_TDO, * LVTH182514_CLK, LVTH182514_CLKENN, LVTH182514_LE, * LVTH182514_OEN, LVTH182514_TCK, * LVTH182514_TDI, LVTH182514_TMS * * PACKAGE PARASITICS .LIB 'PKGS.LIB' TSSOP64 * * PROCESS MODELS .LIB 'EPIC2BSE.LIB' NOMINAL_L13 * .LIB 'EPIC2BSE.LIB' STRONG_L13 * .LIB 'EPIC2BSE.LIB' WEAK_L13 * * LVTH182514_APORT SUBCIRCUIT * (USE FOR PINS - 03, 04, 05, 07, 08, 09, 11, 12, 13, 15 A1..A10; * 16, 17, 18, 20, 21, 22, 24, 25, 26, 27 A11..A20) * * NODES: I/O NODE * | INTERNAL OUTPUT NODE * | | INTERNAL INPUT NODE * | | | INTERNAL OE NODE * | | | | VCC * | | | | | GND * | | | | | | .SUBCKT LVTH182514_APORT 11 12 14 15 199 100 X_PKGIO 11 1001 TSSOP64_03 X_PKGVCC 199 1199 TSSOP64_10 X_PKGGND 100 1100 TSSOP64_06 X_PADIO 1001 1100 LVTH182514__PAD X_PADVCC 1199 1100 LVTH182514__PAD XLVTH182514IN 1001 12 1199 1100 LVTH182514__IBUF XLVTH182514OUT 14 1001 15 1199 1100 LVTH182514__TOB .ENDS LVTH182514_APORT * * LVTH182514_BPORT SUBCIRCUIT * (USE FOR PINS - 62, 61, 60, 58, 57, 56, 54, 53, 52, 50 B1..B10; * 49, 48, 47, 45, 44, 43, 41, 40, 39, 37 B11..B20) * * NODES: I/O NODE * | INTERNAL OUTPUT NODE * | | INTERNAL INPUT NODE * | | | INTERNAL OE NODE * | | | | VCC * | | | | | GND * | | | | | | .SUBCKT LVTH182514_BPORT 11 12 14 15 199 100 X_PKGIO 11 1001 TSSOP64_62 X_PKGVCC 199 1199 TSSOP64_55 X_PKGGND 100 1100 TSSOP64_59 X_PADIO 1001 1100 LVTH182514__PAD X_PADVCC 1199 1100 LVTH182514__PAD XLVTH182514IN 1001 12 1199 1100 LVTH182514__IBUF XLVTH182514OUT 14 1001 15 1199 1100 LVTH182514__T25 .ENDS LVTH182514_BPORT * * LVTH182514_TDO SUBCIRCUIT * (USE FOR PINS - 31 TDO) * * NODES: INTERNAL INPUT NODE * | OUTPUT NODE * | | INTERNAL OE NODE * | | | VCC * | | | | GND * | | | | | .SUBCKT LVTH182514_TDO 4 5 6 199 100 X_PKGOUT 5 1005 TSSOP64_31 X_PKGVCC 199 1199 TSSOP64_23 X_PKGGND 100 1100 TSSOP64_27 X_PADOUT 1005 1100 LVTH182514__PAD X_PADVCC 1199 1100 LVTH182514__PAD XLVTH182514OUT 4 1005 6 1199 1100 LVTH182514__TOB .ENDS LVTH182514_TDO * * LVTH182514_CLK SUBCIRCUIT * (USE FOR PINS - 30 CLKAB, 64 CLKBA) * * NODES: INPUT NODE * | INTERNAL OUTPUT NODE * | | VCC * | | | GND * | | | | .SUBCKT LVTH182514_CLK 1 2 199 100 X_PKGIN 1 1001 TSSOP64_64 X_PKGVCC 199 1199 TSSOP64_10 X_PKGGND 100 1100 TSSOP64_06 X_PADIN 1001 1100 LVTH182514__PAD X_PADVCC 1199 1100 LVTH182514__PAD XLVTH182514IN 1001 2 1199 1100 LVTH182514__ICLK .ENDS LVTH182514_CLK * * LVTH182514_CLKENN SUBCIRCUIT * (USE FOR PINS - 29 CLKENAB\, 63 CLKENBA\) * * NODES: INPUT NODE * | INTERNAL OUTPUT NODE * | | VCC * | | | GND * | | | | .SUBCKT LVTH182514_CLKENN 1 2 199 100 X_PKGIN 1 1001 TSSOP64_01 X_PKGVCC 199 1199 TSSOP64_10 X_PKGGND 100 1100 TSSOP64_06 X_PADIN 1001 1100 LVTH182514__PAD X_PADVCC 1199 1100 LVTH182514__PAD XLVTH182514IN 1001 2 1199 1100 LVTH182514__ICLK .ENDS LVTH182514_CLKENN * * LVTH182514_LE SUBCIRCUIT * (USE FOR PINS - 35 LEAB, 01 LEBA) * * NODES: INPUT NODE * | INTERNAL OUTPUT NODE * | | VCC * | | | GND * | | | | .SUBCKT LVTH182514_LE 1 2 199 100 X_PKGIN 1 1001 TSSOP64_63 X_PKGVCC 199 1199 TSSOP64_10 X_PKGGND 100 1100 TSSOP64_06 X_PADIN 1001 1100 LVTH182514__PAD X_PADVCC 1199 1100 LVTH182514__PAD XLVTH182514IN 1001 2 1199 1100 LVTH182514__ICLK .ENDS LVTH182514_LE * * LVTH182514_OEN SUBCIRCUIT * (USE FOR PINS - 36 OEAB\, 02 OEBA\) * * NODES: INPUT NODE * | INTERNAL OUTPUT NODE * | | VCC * | | | GND * | | | | .SUBCKT LVTH182514_OEN 1 2 199 100 X_PKGIN 1 1001 TSSOP64_02 X_PKGVCC 199 1199 TSSOP64_10 X_PKGGND 100 1100 TSSOP64_06 X_PADIN 1001 1100 LVTH182514__PAD X_PADVCC 1199 1100 LVTH182514__PAD XLVTH182514IN 1001 2 1199 1100 LVTH182514__INUP .ENDS LVTH182514_OEN * * LVTH182514_TCK SUBCIRCUIT * (USE FOR PINS - 33 TCK) * * NODES: INPUT NODE * | INTERNAL OUTPUT NODE * | | VCC * | | | GND * | | | | .SUBCKT LVTH182514_TCK 1 2 199 100 X_PKGIN 1 1001 TSSOP64_33 X_PKGVCC 199 1199 TSSOP64_23 X_PKGGND 100 1100 TSSOP64_27 X_PADIN 1001 1100 LVTH182514__PAD X_PADVCC 1199 1100 LVTH182514__PAD XLVTH182514IN 1001 2 1199 1100 LVTH182514__ITCK .ENDS LVTH182514_TCK * * LVTH182514_TDI SUBCIRCUIT * (USE FOR PINS - 34 TDI) * * NODES: INPUT NODE * | INTERNAL OUTPUT NODE * | | VCC * | | | GND * | | | | .SUBCKT LVTH182514_TDI 1 2 199 100 X_PKGIN 1 1001 TSSOP64_34 X_PKGVCC 199 1199 TSSOP64_23 X_PKGGND 100 1100 TSSOP64_27 X_PADIN 1001 1100 LVTH182514__PAD X_PADVCC 1199 1100 LVTH182514__PAD XLVTH182514IN 1001 2 1199 1100 LVTH182514__INUP .ENDS LVTH182514_TDI * * LVTH182514_TMS SUBCIRCUIT * (USE FOR PINS - 32 TMS) * * NODES: INPUT NODE * | INTERNAL OUTPUT NODE * | | VCC * | | | GND * | | | | .SUBCKT LVTH182514_TMS 1 2 199 100 X_PKGIN 1 1001 TSSOP64_32 X_PKGVCC 199 1199 TSSOP64_23 X_PKGGND 100 1100 TSSOP64_27 X_PADIN 1001 1100 LVTH182514__PAD X_PADVCC 1199 1100 LVTH182514__PAD XLVTH182514IN 1001 2 1199 1100 LVTH182514__INUP .ENDS LVTH182514_TMS * * .SUBCKT LVTH182514__PAD 801 800 * pad.lvta (97212 ALEY) D1 800 801 QESD 1 CPAD 801 800 0.3P .ENDS LVTH182514__PAD * .SUBCKT LVTH182514__IBUF 501 502 599 500 * ibuf.lvta (97212 ALEY) XN1 503 500 500 500 NM WN=100U LN=0.7U XN2 504 502 500 500 NM WN=4U LN=1.7U XP1 505 502 599 599 PM WP=11U LP=0.7U XNINV1 502 506 500 500 NM WN=8U LN=0.7U XPINV1 502 506 599 599 PM WP=24U LP=0.7U XNINV2 506 502 500 500 NM WN=4U LN=0.7U XPINV2 506 502 599 599 PM WP=10U LP=0.7U XNINV3 502 503 500 500 NM WN=142U LN=0.7U XPINV3 502 503 599 599 PM WP=300U LP=0.7U XR41 503 507 504 507 RMOS WR=6.5U RES=1K D1 599 507 D100 10.5 D2 505 504 D100 150 R1 501 503 80 CL 502 500 0.1P .ENDS LVTH182514__IBUF * .SUBCKT LVTH182514__ICLK 501 502 599 500 * iclk.lvta (97212 ALEY) XN1 503 500 500 500 NM WN=100U LN=0.7U XPINV1 502 504 599 599 PM WP=30U LP=0.7U XNINV2 504 502 500 500 NM WN=4U LN=0.7U XPINV2 504 502 599 599 PM WP=10U LP=0.7U XNINV3 502 503 500 500 NM WN=190U LN=0.7U XPINV3 502 503 599 599 PM WP=400U LP=0.7U R1 501 503 80 CL 502 500 0.1P .ENDS LVTH182514__ICLK * .SUBCKT LVTH182514__INUP 501 502 599 500 * inup.lvta (97212 ALEY) XN1 503 500 500 500 NM WN=100U LN=0.7U XPINV1 502 504 599 599 PM WP=30U LP=0.7U XNINV2 504 502 500 500 NM WN=4U LN=0.7U XPINV2 504 502 599 599 PM WP=10U LP=0.7U XNINV3 502 503 500 500 NM WN=190U LN=0.7U XPINV3 502 503 599 599 PM WP=400U LP=0.7U XR41 505 599 599 599 RMOS WR=3.0U RES=60K D1 505 503 D100 100 R1 501 503 80 CL 502 500 0.1P .ENDS LVTH182514__INUP * .SUBCKT LVTH182514__ITCK 501 502 599 500 * itck.lvta (97212 ALEY) XN1 503 500 500 500 NM WN=100U LN=0.7U XPINV1 502 504 599 599 PM WP=24U LP=0.7U XNINV2 504 502 500 500 NM WN=4U LN=0.7U XPINV2 504 502 599 599 PM WP=10U LP=0.7U XNINV3 502 503 500 500 NM WN=142U LN=0.7U XPINV3 502 503 599 599 PM WP=300U LP=0.7U R1 501 503 80 CL 502 500 0.1P .ENDS LVTH182514__ITCK * .SUBCKT LVTH182514__TOB 601 602 603 699 600 * tob.lvta (97212 ALEY) XN1 606 606 606 600 NM WN=10U LN=0.7U XN2 607 604 600 600 NM WN=75U LN=0.7U XN3 608 605 607 600 NM WN=75U LN=0.7U XN4 699 609 610 600 NM WN=100U LN=0.7U XN5 610 605 611 600 NM WN=250U LN=0.7U XN6 612 613 600 600 NM WN=100U LN=0.7U XN7 613 603 600 600 NM WN=30U LN=0.7U XN8 613 614 601 600 NM WN=20U LN=0.7U XN9 609 630 615 600 NM WN=10U LN=0.7U XN10 616 603 600 600 NM WN=30U LN=0.7U XN11 616 601 600 600 NM WN=30U LN=0.7U XN12 611 601 617 600 NM WN=250U LN=0.7U XN13 617 603 600 600 NM WN=60U LN=0.7U XN14 617 604 600 600 NM WN=60U LN=0.7U XN15 701 701 600 600 NM WN=10U LN=0.7U XP1 619 604 699 699 PM WP=150U LP=0.7U XP2 620 605 699 699 PM WP=150U LP=0.7U XP3 699 603 621 699 PM WP=100U LP=0.7U XP4 613 603 601 699 PM WP=40U LP=0.7U XP5 622 603 699 699 PM WP=30U LP=0.7U XP6 616 601 621 699 PM WP=100U LP=0.7U XP41 602 631 618 618 PM WP=10U LP=0.7U XP42 602 699 618 618 PM WP=50U LP=0.7U XP43 602 608 699 618 PM WP=1300U LP=0.7U XP44 602 699 608 618 PM WP=50U LP=0.7U XP45 602 631 608 618 PM WP=10U LP=0.7U XNINV1 605 603 600 600 NM WN=80U LN=0.7U XPINV1 605 603 699 699 PM WP=160U LP=0.7U XNINV2 614 603 600 600 NM WN=5U LN=0.7U XPINV2 614 603 699 699 PM WP=15U LP=0.7U XNINV3 604 601 600 600 NM WN=50U LN=0.7U XPINV3 604 601 699 699 PM WP=60U LP=0.7U XR41 610 699 699 699 RMOS WR=6U RES=4.5K XR42 609 622 622 622 RMOS WR=4U RES=12K XR43 701 631 702 631 RMOS WR=4U RES=2K XR44 702 631 703 631 RMOS WR=4U RES=2K XR45 703 631 704 631 RMOS WR=4U RES=2K XR46 704 631 705 631 RMOS WR=4U RES=2K XR47 705 631 630 631 RMOS WR=4U RES=12.5K XR48 630 631 631 631 RMOS WR=4U RES=50K Q1 699 603 620 Q2_NPN 10 Q2 699 601 619 Q2_NPN 10 Q3 623 616 624 Q2_NPN 10 Q4 623 624 602 Q100 100 Q5 602 617 600 Q300 300 QD1 624 624 616 Q1_NPN 5 D1 699 618 D100 150 D2 619 608 D400 306 D3 620 608 D400 306 D4 617 602 D900 700 D5 699 623 D900 800 D6 699 623 D900 800 D7 616 623 D100 100 D8 699 631 D100 150 R1 615 602 100 R2 602 612 100 .ENDS LVTH182514__TOB * .SUBCKT LVTH182514__T25 601 602 603 699 600 * t25.lvta (97212 ALEY) XN1 606 606 606 600 NM WN=10U LN=0.7U XN2 607 604 600 600 NM WN=75U LN=0.7U XN3 608 605 607 600 NM WN=75U LN=0.7U XN4 699 609 610 600 NM WN=100U LN=0.7U XN5 610 605 611 600 NM WN=250U LN=0.7U XN6 612 613 600 600 NM WN=100U LN=0.7U XN7 613 603 600 600 NM WN=30U LN=0.7U XN8 613 614 601 600 NM WN=20U LN=0.7U XN9 609 630 615 600 NM WN=10U LN=0.7U XN10 616 603 600 600 NM WN=30U LN=0.7U XN11 616 601 600 600 NM WN=30U LN=0.7U XN12 611 601 617 600 NM WN=250U LN=0.7U XN13 617 603 600 600 NM WN=60U LN=0.7U XN14 617 604 600 600 NM WN=60U LN=0.7U XN15 701 701 600 600 NM WN=10U LN=0.7U XP1 618 604 699 699 PM WP=150U LP=0.7U XP2 619 605 699 699 PM WP=150U LP=0.7U XP3 699 603 620 699 PM WP=100U LP=0.7U XP4 613 603 601 699 PM WP=40U LP=0.7U XP5 621 603 699 699 PM WP=30U LP=0.7U XP6 616 601 620 699 PM WP=100U LP=0.7U XP41 622 631 623 623 PM WP=10U LP=0.7U XP42 622 699 623 623 PM WP=50U LP=0.7U XP43 622 608 699 623 PM WP=1300U LP=0.7U XP44 622 699 608 623 PM WP=50U LP=0.7U XP45 622 631 608 623 PM WP=10U LP=0.7U XNINV1 605 603 600 600 NM WN=80U LN=0.7U XPINV1 605 603 699 699 PM WP=160U LP=0.7U XNINV2 614 603 600 600 NM WN=5U LN=0.7U XPINV2 614 603 699 699 PM WP=15U LP=0.7U XNINV3 604 601 600 600 NM WN=50U LN=0.7U XPINV3 604 601 699 699 PM WP=60U LP=0.7U XR41 610 699 699 699 RMOS WR=6U RES=4.5K XR42 609 621 621 621 RMOS WR=4U RES=12K XR43 701 631 702 631 RMOS WR=4U RES=2K XR44 702 631 703 631 RMOS WR=4U RES=2K XR45 703 631 704 631 RMOS WR=4U RES=2K XR46 704 631 705 631 RMOS WR=4U RES=2K XR47 705 631 630 631 RMOS WR=4U RES=12.5K XR48 630 631 631 631 RMOS WR=4U RES=50K Q1 699 603 619 Q2_NPN 10 Q2 699 601 618 Q2_NPN 10 Q3 624 616 625 Q2_NPN 10 Q4 624 625 622 Q100 100 Q5 622 617 600 Q300 300 QD1 625 625 616 Q1_NPN 5 D1 699 623 D100 150 D2 618 608 D400 306 D3 619 608 D400 306 D4 617 622 D900 700 D5 699 624 D900 800 D6 699 624 D900 800 D7 616 624 D100 100 D8 699 631 D100 150 R1 622 602 25 R2 615 622 100 R3 622 612 100 .ENDS LVTH182514__T25 * LVTH182514_97213AL