Tactical Missiles DSP System Features

Performs parallel multiply and ALU operations on integer or floating point data in a single cycle. The processor also possesses a general purpose register file, program cache, dedicated auxiliary register arithmetic units, internal dual access memories, one DMA channel supporting concurrent I/O, and a short machine-cycle time. High performance and ease of use are benefits of these features.
Missile applications are greatly enhanced by the large address space, internally and externally generated wait states, two external interface ports, two timers, two serial ports, and multiple interrupt structure.
High level language support is more easily implemented through a register based architecture, large address space, powerful addressing modes, flexible instruction set, and well supported floating point arithmetic.
Fully validated Ada compiler available.
33 and 40 MFLOPS versions are available to meet high speed requirements.
Packaging includes CQFP, CPGA, KGD, and TAB.
SMD approval.

Designed for parallel processing with six communication ports, this makes the immense floating point performance required for target recognition and imaging achievable and cost effective.
High degree of integration results in smaller, lighter modules.
Fully validated Ada compiler available.
33 and 40 MFLOPS versions are available.
Packaging includes CQFP, CPGA, MCM, KGD, and TAB.
SMD approval.

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