Question: In the 1993 C5X User's Guide, pg. 3-34 and 3-35, there's a statement that talks about memory mapped accesses to load AR registers. It lists instructions like SAMM, LMMR, SACL, and SPLK. Should the TBLR instruction be treated the same as these instructions?

Answer: Yes, using the TBLR instruction to load an AR register will actually load the register in the execute phase of the pipeline. If the next instruction uses indirect addressing with that AR register, the address will be generated in the decode phase of the pipeline; hence a pipeline discrepancy.