Question: I am trying to find a way of using SDRAM with a 50 MHz C80. I have a copy of the SDRAM Application Report (preliminary Data) dated 25/5/95. It seems to suggest that single cycle access is not possible without incurring violations on the setup and access times to the SDRAM. I therefore have the following questions:

1. Is this still true, or are there more up to date timings that do not show violations? Or have you found this to not be a problem on the reference design mentioned in this report?
2. Is there a way of inserting wait states into the SDRAM access to provide a 2 cycle access with no timing violations.
3. Do you have any other suggestions as to how single or dual cycle access can be achieved without timing violations.

Answer:
1. There is an update to the SDRAM Ap report, which is available. The timings however have not changed, and yes, there are timing violations in the report. The reference design board that we have built does work at 50MHz though, if that gives you any encouragement. From a product standpoint, if you don't have a lot of memory out there to load the bus, you could get by without the buffers and eliminate any violations at all. Also, you can use CBT buffers which will handle the 3.3 to 5V conversion if necessary, and specify sub-ns delays. These parts have no drive capability, but if you are not loading the bus heavily things will be fine.
2. No, the JEDEC standard does not even allow for this to occur, since the SDRAM is by definition a clocked EDO type memory.
3. Yes, remove the buffers or use CBT parts. If you need the additional drive of the LVT buffers, you might want to consider using a small PLL to drive the SDRAM CLK inputs.