Question: The two bit status field is used to signal an end of packet transfer, when in the bus cycle is this code asserted? Coincident with RL? or at the very end of the cycle? :

Answer: No, it is asserted during the final column access of the XPT. One extra note- if the XPT is ext-ext, then it will actually be asserted twice- once for the read and once for the write. You can use the /W signal to additionally qualify which "end" you are seeing if your system requires it (IE. /W high and XPT end is not really the end, /W low with XPT end is on ext-ext transfers)


Device: TMS320C8x
Category: Related Devices
Detail: Memory Interfaces
Title: When in the Bus Cycle is this Code Asserted
Source: Case from TMS320 Hotline
Date: 8/1/97
GenId: 0008018

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