Question:
1) Can the DRAM be examined while the MP is halted debugger/code while using the SDB API library?
2) If not, then can the SDB API library examine the DRAM?
3) If not, then can the SDB API kernel be incorporated into their code?

Answer:
1) No, there is no direct path between the host and the SDB DRAM through PCI. The only interface is 32k of board i/o space and 32k mapped to the PCI FIFO. In order for the host to access the SDB DRAM, it has to send a command to the C80 through the PCI FIFO via EINT3 then the C80 must execute a server command which completes the access. For example, if the host wants to read one word from SDB DRAM, the following things happen: - host writes the server 'read' command in the the PCI FIFO - host causes EINT3 on the C80 - C80 services EINT3 in which the ISR is the server - the server ISR reads the command out of the FIFO - the server decodes the command as a DRAM read - the server reads the DRAM then writes it into the FIFO - the server notifies the host that data is ready in the FIFO - host reads data from FIFO If the C80 is halted, the ISR never executes, hence, no data written into the FIFO for the host to read. If the host reads an empty FIFO, it causes and undesirable bus lock.
2) see answer 1
3) No, the SDB API kernel is TI third party proprietary.