 Interrupts
To reduce external logic and simplify the interface,
the external interrupts are edge or level triggered. To
provide more flexibility in the placement of interrupts,
the C32 interrupts are relocatable.
Edge or Level Triggered Interrupts
Edge- or level- triggered interrupts are selectable
through the INT Config bit field in the Status
Register. This field can have the following values:
- 0 Level
Triggered Interrupts
- All the external interrupts, INT3-INT0, are
configured as level trigger interrupts.
Multiple interrupts may be triggered when the
signal is active for a long period of time.
- 1 Edge Triggered
Interrupts
- All the external interrupts, INT3-INT0, are
configured as edge trigger interrupts. Edge
and duration are required for the interrupt
to be recognized.
Status
Register
Relocatable Interrupts
Unlike the fixed interrupt-trap vector table location
of the 'C30 and 'C31 devices, the 'C32 has a user
relocatable interrupt-trap vector table. The
interrupt-trap vector table must start on a 256-word
boundary. The starting location is programmable through
the Interrupt-Trap Table Pointer (ITTP) bit field
in the CPU Interrupt Flag Register (IF).
Interrupt Flag Register
The ITTP bit field dictates the starting location
(base) of the interrupt-trap vector table. This base
address is formed by left-shifting by 8 bits the value of
the ITTP bit field. This shifted value is called the effective
base address and is referenced as EA[ITTP], as
shown in following figure. Therefore, the location of an
interrupt or trap vector is given by the addition of the
effective base address formed by the ITTP bit field
(EA[ITTP]) and the offset of the interrupt or trap vector
in the Interrupt-Trap Vector Table. For example, if the
ITTP contains the value 100h, the serial port transmit
interrupt vector will be located at 10005h.
Note that the vectors stored in
the Interrupt-Trap Vector Table are the addresses of the
start of the respective interrupt and trap routines.
Furthermore, the Interrupt-Trap Vector Table must lie on
a 256-word boundary since the eighth least significant
bits of the effective base address of the Interrupt-Trap
Vector Table are zero.
Effective Base Address of the
Interrupt-Trap Vector Table
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