External Interface Operation Overview

The TMS320C32 memory interface accesses external memory through one 24-bit address bus and one 32-bit data bus that is shared by three mutually exclusive strobes (STRB0, STRB1, and IOSTRB). Each strobe's configuration is independent of the physical memory width and data size, and also independent of the other strobe's configuration.

Depending on the address accessed, the TMS320C32 activates one of these strobes according to the following Memory Map:

External Interface Features

TMS320C32's external memory interface includes the following features:

• One external pin, PRGW, configures the external program memory width to 16 or 32 bits.
• Two sets of memory STRBs (STRB0 and STRB1) and one IOSTRB allow zero glue logic interface to two banks of memory and one bank of external peripherals.
• Separate bus control registers for each STRB control wait state generation, external memory width, and data type size.
• Each memory STRB (STRB0 and STRB1) handles 8, 16 or 32 bit external data accesses (reads and writes).
• Each memory STRB (STRB0 and STRB1) handles 8, 16 or 32 bit external memory widths.
• IOSTRB accesses 32 bit data from 32 bit wide memory. IOSTRB bus cycles are different than STRB0 and STRB1's bus cycles to accommodates slower I/O peripherals.
• Multi-processor support through the HOLD and HOLDA signals is valid for all the STRBs.