Question: Wants to use SMQ320C32 in 16 bit bus mode.
He needs to know if it is critical to NOT terminate the unused 16 data signals.

Answer: Pull-up/downs are not required unless ultra low power consumption in shutdown (IDLE2) mode is required.
If left floating, this could result in several mA of trickle current. I don't believe in this case that you are needing pull-up/downs for other reasons, like sign extending or zeroing a field.

The C3x/C4x family does not have internal bus keeper circuits, but there are several simple workarounds that may work just as well as pull-up pulldown.

Capactive hold on bus

As long as there are no major leakage currents on the dbus pins, the last driven value can hang around for an amazingly long time (100"s of uS are not untypical).

If for example the total bus capacitance is 50pF, and the total leakage current is 10uA (quite high),
the slew time (dT) to move away from a valid to invalid level can be calculated from:

I=C*dV/dT I=10uA, dV=1V, C=50pF ---> dT=C*dV/I = 5uS

Software trick for C3x/C4x
--------------------------
If the CPU is used to perform a multicycle write just before the IDLE2 condition is encountered, that write will essentially become "frozen" as the CPU halts. Since the data pins are actively driven, the bus state will be held indefinitely. Below is the example code taken from the C31 DSK applications. In this case, the CPU is executing from internal RAM, but it should also work if execution is from external SRAM, as long as the write operation is posted at the proper time.

MORE INFORMATION

;---------------------------------------------------------------------
; IDLE2.ASM
; Keith Larson
; TMS320 DSP Applications
; (C) Copyright 1995,1996
; Texas Instruments Incorporated
;
; This is unsupported freeware with no implied warranties or
; liabilities.  See the disclaimer document for details
;
; This code shows a feature of the C31 where IDLE2 can be used to
; freeze the external bus during a data write.  If used properly
; this can eliminate the need for 32 data bus pull-up/down resistors
;
; To use this feature the value being written to external bus must
; be in the middle of a write cycle when the IDLE2 executes.  This
; may require shuffling the opcodes around a little depending on
; the bus control register setup.
;---------------------------------------------------------------------
        .start CODE,0x809802 ; Start assembling CODE section here
        .sect  CODE          ;
        .entry  SAMPLE         ; Debugger entry point
        ;----------------------
SAMPLE  ldp     @stack         ; Load a data page
        ldi     @stack,SP      ; Load a stack pointer
        ;----------------------
        ldi     0,R0           ; Load all 0"s into R0
        ldi     0x4000,AR0     ; Load AR0=0x8000 with an external address
        lsh     1,AR0          ;
        ;----------------------
LOOP    not    R0,R0           ; Invert all bits
        call   LOZBUS          ; Freeze R0 value on bus while in IDLE2
        call   HIZBUS          ; Execute an IDLE2 normally (bus is tri-state)
        b      LOOP            ;
        ;----------------------
LOZBUS  sti    R0,*AR0         ; Write bit pattern to the external bus
     ;  nop                    ; more code depending on bus setup
     ;  nop                    ;
        idle2                  ; Freeze operation during a multicycle write
        rets                   ;
        ;----------------------
HIZBUS  idle2                  ; Freeze operation - No write
        rets                   ;
        ;----------------------
stack   .word   $
        .end