Question: There are various clock options on the C52, but I am really only asking about the NON PLL options. What I am trying to do is find out about the relationship between CLKIN and CLKOUT2. If you take the 100 MHz C52 and put 100MHz crystal across X1 and X2 you choose the internal divide by 2 and get a device system clock of 50 MHz, this will appear as CLKOUT1. The rising edge of this CLKOUT signal is delayed with respect to the CLKIN rising edge by anything between 1 to 18 ns according to the datasheet. Now if you do the divide by 2 externally and feed this directly in on the X2/CLKIN pin and have CLKMD1 and CLKMD2 both set to 0 i.e. external divide by 2 with internal oscillator disabled, does this mean that CLKOUT1 is fed directly by CLKIN signal so that the delay between rising edge of CLKOUT signal with respect to the CLKIN rising edge is effectively zero. My thinking here is the because the CLOCK does not have to go via the internal oscillator as it is disabled. I appreciate there may be a delay due to buffering the signal out of the chip but this will be negligible. Can someone tell me whether my thinking is correct here. And if my thinking here is correct what will delay be between CLKIN rise time and CLKOUT1 rise time, max and min.

Answer: This is not correct. In any of the clock modes called divide-by-2, the CLKIN is divided by 2 internally and fed to CLKOUT1. The external vs. internal refers to whether you will provide a clock signal externally, or whether you will attach a crystal to generate a clock using the on-chip oscillator. The option of enabling or disabling the oscillator basically disables the inverter that runs to pin X1 which is used to drive the crystal. So the time delay between X2/CLKIN transitions and CLKOUT1 transitions will be the same regardless of how the X2/CLKIN transitions are generated.