Question: Could somebody provide an example of boot load schematics?
One of our customers is designing an application using C32 dsp (40MHz) which interfaced to 256k x 8 bits EEPROM (150ns) and 4 x 8 bits wide x 32k SRAM (10ns).

He is trying to bootload from EEPROM to external SRAM.

Answer: The C32 architecture is quite flexible. Unlike the C31, the C32 has 3 separate strobe spaces, which are independent from each other. When the bootloader is enabled (execution from an internal bootrom) the bootrom device can be enabled from any of the STRB0, STRB1, or IOSTRB spaces. What you need to do is identify how complex the rest of the system is in terms of mapped SRAM or IO devices. Your description appears to be a simple, consisting of a bootrom, SRAM and maybe a serial codec. In this case, enabling the SRAM bytes using STRB0_B0->STRB0_B3 and the bootrom from either STRB1 or IOSTRB would be a good choice. This will map the SRAM to be contiguous with the end of the internal SRAM allowing your code or data to grow out of fast internal SRAM and into the slower SRAM maximizing performance. To boot the device, pull down the appropriate INTx lines (permanently?) and MCBL mode pin, and hit reset.