Question: Recommendations we may have regarding PWB layout and design for the clock circuit for the C6201, considering that it will be oscillating at very high frequencies.

Answer: A few suggestions:

1. Keep the clock traces as short (and preferably wide)
   
2. Choice of external clock crystal should be made keeping in mind the FCC manifestations of a higher external clock frequency. In short, use the PLL option which will allow you to use a slower external crystal
   
3. Using ground planes - this will have cost manifestations too. In my experience, it is safer to have separate ground and Vcc planes than not having them at all.
   
4. Keep address (and data) lines short
   
5. If this is a mixed signal design, please please isolate the analog circuits from the digital circuits
   
6. Some crystal manufacturers provide a third ground pin (on the crystal) - that is sometimes useful to have, although not mandatory.
   
7. Avoid right angled traces - these act as good antennas, and you don"t want that to happen :) Best traces are 45 degrees (in case you did want the traces to curve)...
   
8. Sometimes damping resistors (5 to 10 ohms) are useful on address lines, but this should be your absolutely last option because it is costly (definition of cost differs from one designer to another), and designers do not like it