Question: Can you please confirm if the timing diagrams of the READY signal are correct? Looking at page 73 of the July 97 datasheet it really looks like MSC_ is active on the first internal wait state cycle and not on the second.

Answer: The timing diagrams of the READY signal are correct. One of the note states that ...READY is not sampled until the completion of the INTERNAL software wait states..... I think the wording is kind of confusing people here. What's going on here is the software wait state cycle internally happens one cycle earlier than the ones you see it happens externally as shown in those timing diagrams. And the note should state that ...READY is not sampled until the software wait state cycle completes internally....