Question: How many cycles(as fast as possible) for an 8-bit data from Host to HPI dual-access RAM in the SAM mode for 100MIPS C54x? 2- Can C54x access the DARAM, and Host transfer the data to DARAM simultaneous?

Answer: In SAM, the HPI can perform 1 access(8-bit) every 5 DSP clock cycles. Since the HPI can be set up to perform auto-incrementing, you can keep feeding it data once you get started and don"t have to provide address information with each data.

This should yield 8 bits every 5 clock cycles ==> 20MB/sec (160Mb/s) at 100MHz

The DSP can access the DARAM at the same time as the host, but the host has priority. So, the host is accessing at the maximum rate, it could hold off the DSP as often as every 5 cycles, depending on how constant the access is from the DSP.