Pipeline conflict in fetch phase

If a pipeline conflict exists during the fetch phase, the instruction will be refetched from memory (if the cache is disabled) or from cache (if the cache is enabled). If from memory, this may cause further pipeline conflicts.


Device: TMS320C4x
Category: Device Information
Detail: Registers
Title: Pipeline conflict in fetch phase
Source: Case from the TMS320 Hotline
Date: 4/30/98
GenId: a3

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