Memory read / write and the pipeline

A memory write operation takes always 1 CYCLE under the CPU/DMA point, even if it involves wait-states: in the first cycle the CPU/DMA writes into the memory bus and can continue execution without any need to wait for the write operation to complete. However if there is an access to the same external bus before the write operation completes, the pipeline halts.   A memory read operation has to wait for the entire read operation to complete before proceeding to the next pipeline stage and may halt the pipeline meanwhile.