'C3x
DSK Daugthercard with external EPROM
An external boot EPROM or EEPROM can be added to the DSK by using the /UBOOT enable pin
to enable a device in the range of 0x000000 to 0x100000 which corresponds to a bootload
select using INT0. The TMS320C31 bootloader is actually DSP code that is contained in a
pre-programmed ROM internal to the chip. The internal bootloader code space is mapped to
0x0000-0xFFFF and is enabled by MCBL/MP=1, which is the default for the DSK. The internal
bootloader is used for normal DSK operation as well as EPROM Bootloading so there is no
need to change the value of MCBL/MP.
When an INT0 bootload is selected, the internal bootloader code causes the DSP to read
the first external byte value (the code you want to bootload) from address 0x1000. Other
interrupts select different address ranges. For example, INT2 which the DSK used for host
communications is also used to bootload the DSK kernel from the host interface.
If your EPROM decodes an address range less than 0x1000, you can use memory aliasing to
access your bootcode at ROM_address=0x0000. You can do this with a larger EPROM by tying
the upper EPROM address lines low, but this wastes EPROM space. Memory aliasing works
because the external ROM is enabled over many pages, one of which is at 0x1000.
If your EPROM decode range is greater than 0x1000, you will need to copy/load your
bootcode at an offset of 0x1000 in the EPROM. The lower 0x1000 of space can still be
accessed using an aliased memory page.
The number of software wait states defined in the bus control register must be
sufficient for the speed of the EPROM that you use plus the delay time for the /UBOOT
signal to decode. For example, if you use an 85 nS EPROM, and the decoder takes 25 nS,
plus DSP signal delay of 13 nS, You will need 123 nS of bus cycle time. With three wait
states the bus read time is (3+1)*40 nS = 160 nS which ensures proper operation. In
practice, if the devices are operated at or near room temperature, which widens the timing
margins substantially, fewer cycles may work, but it is not suggested.
The DSK host interface also requires at least one wait state to operate properly. Do
not lower the wait states below this value if you plan to also use the DSK debugger. Since
DSK bootloaded code primarily runs in the on-chip memory, any value of wait states will
work without degrading performance.
The DSK3D debugger can be used even if an external EPROM is used. The only constraint
is that the first bootloader select interrupt after reset is applied will determine which
bootsource will be used
If the printer port is not connected, or if the DSK debugger (or other application) is
not executing a command, the INT2 line will be inactive high. By then pulsing /RESET low,
followed by INT0 low, the TMS320C31 will execute a bootload operation from address 0x1000.
Typical (E)EPROM circuit
DSK HEADERS 8 bit (E)EPROM
Vcc
|
JP6 Rp +------------+
+--+ #J1 | | |
/UBOOT| 4|---x-x--*----|/CE | #Jumpers J1 & J2 are either
| | #J2 | | both installed or removed
PWM| 9|---x-x--+ | |
+--+ | | | *A R/W connection is only
/// | | needed for an EEPROM
JP3 Gnd | |
+--+ | | Other chip enables may need
A0|32|-------------|A0 | be tied to logic high or low
A1|31|-------------|A1 |
.| .|-------------| . |
AN|??|-------------|AN (size?) |
+--+ | |
JP5 | |
+--+ | |
D0|32|-------------|D0 |
D1|31|-------------|D1 |
.| .|-------------| . |
D7|25|-------------|D7 |
+--+ Vcc | |
| | |
JP2 Rp | |
+--+ *J3 | | |
R/W|21|---x-x--*----|R/W (EEPROM)|
+--+ | |
+------------+
|