Question: Interfacing SRAM with a VC549-100

To achieve computation power needs and external memory size constraints, it tries to adapt the DSP frequency to external SRAM access timings. They intend to use 8 ns access time SRAM chips. In order to find out the maximum working frequency 2 methods are used and are described here below:

1) The purpose is to accumulate Td(CLKL-MSL) max with Tsu(D)R min and Taa the access time of the SRAM. Therefore Fmax = 1/(Td(CLKL-MSL)+Tsu(D)R+Taa)

2)The purpose is to accumulate Ta(A)M max with Taa Thus Fmax = 1/(Ta(A)M+Taa) According to the oldest D/S they have (April 97 !?)

same result is achieved for both 1) and 2) options: Fmax = 76.9 MHz Now, same calculation has been done with January 98 timings and 2 different results are achieved !! Fmax1 = 66.6 MHz ( 1st formula ) Fmax2 = 71.4 MHz ( 2nd formula )

Answer: First - the correct answer is 71.428 MIPS for an 8 ns memory used with a VC549-100 (note that this is independent of any other factors in the system). The reason that approach 1) does not yield the correct answer is a similar one to many questions asked in the past: it will virtually always yield an excessively conservative result when you calculate timings from multiple data sheet parameters. The general rule is - if the parameter you are interested in is spec"d, don"t try to calculate it. The reason that the calculated answers are invalid is that the worst case of each of the timings added together will not occur at the same time on the same device. In your case, you are working with ta(A)M and/or ta(MSTRBL), which are spec"d (2H-6) so don"t try to calculate them. The proper answer is obtained by calculating fmax from the most current data sheet values for ta(A)M/ta(MSTRBL) which are (as above) 2H-6, which yields 71.428 MIPS. The values in the current data sheet (SPRS039B) are the best numbers we have at this time.