What are the differences between SRAM, SSRAM, SBSRAM, FPM, EDO, SDRAM, and SGRAM memories?

Static Random Access Memory (SRAM)

Typically, our DSP devices are designed to interface with static memories due to their fast random access of data. Static memories do not loose information as long as the memory is powered since they store information on flip-flops. They are more expensive than DRAM, but they have faster access times.

Synchronous Static RAM (SSRAM)

The operations performed by a processor are coordinated by an internal clock, but memory access has traditionally used its own fixed timers for reading and writing data. Rather than synchronizing its actions with those of the internal clock, memory access had set times for reading and writing data regardless of the actual time the processes required. This time would normally depend on the delay between a valid address and the time the memory devices produce the corresponding data value. This would sometimes result in periods of wait cycles where nothing was happening. Because of this, memory was considered to be "asynchronous".

However, Synchronous Static Random Access Memory (SSRAM) eliminates this difference between memory speed and processor speed because SSRAM has a clock synchronized with the processor's clock. Address is typically provided in one clock and the corresponding data is provided on the next clock edge, basically pipelining the memory output and synchronizing it to a clock.

Synchronous Burst Static RAM (SBSRAM)

SyncBurst SRAM (SBSRAM) is an extension of the SSRAM by incorporating a small amount of logic that allows the memory to self-cycle through sequential locations, thus providing higher speed operation. Memories of this type also provide four-address burst sequence that is interleaved for Intel compatibility or linear for PowerPC and other microprocessors. Memories of this type can also employing input or output registers that pipeline the SRAM. Loading the registers takes an extra lead-off cycle, but once loaded, it allows early access to the next address location while supplying data from the current location.

Here are two links for Micron Application Notes on interfacing SyncBurst SRAM to C32 and C44:

• C32: TN-58-10 Application Diversity of SyncBurst SRAMs
• C44: TN-58-05 SyncBurst SRAMs in DSP Applications

Dynamic Random Memories (DRAM)

Dynamic RAM store information on capacitors whose charge is lost over time and therefore must be periodically refreshed to maintain the stored information. Due to the simplicity of their design, the are much cheaper than SRAM but suffer from slower access times than SRAM.

Fast Page Memory (FPM) DRAM

FPM (Fast Page Memory) is a dynamic random access memory (DRMA) where a specific location in a memory chip is identified by the row and the column addresses. Each time memory is accessed, the memory controller first supplies the chip with the row address and then the column address. After the information obtained from these locations is validated, the column deactivates and gets ready for the next cycle. This introduces a wait state because nothing is happening while the column is deactivating. The processor must wait for the memory to complete the cycle.

The Fast-Paged Memory (FPM) chip decreased the time required to read these addresses by allowing the memory controller to select a particular row and then access the corresponding column addresses for that row. This process works under the assumption that the next piece of data needed is in the memory location adjacent to the previous piece. Because the row address is only set up once and only the column address changes, this saves time when reading or writing information to or from memory.

Extended Data Out (EDO) DRAM

EDO (Extended Data Out) DRAM is a subset of FPM memory that saves the memory controller even more time by allowing it to begin locating the row and column for the next address, while reading the data at the first address. It is able to do this because EDO memory keeps the output buffer on while preparing for the next read operation. By keeping the buffer on, EDO eliminates wait states. This speeds up data transfer rates since EDO RAM can access data continuously without waiting for addresses to be located. This reduces the time of the read cycles by approximately 10%. However, during write cycles, the system behaves exactly as an FPM chip would behave.

Synchronous DRAM (SDRAM)

The operations performed by a processor are coordinated by an internal clock, but memory access has traditionally used its own fixed timers for reading and writing data. Rather than synchronizing its actions with those of the internal clock, memory access had set times for reading and writing data regardless of the actual time the processes required. This time would normally depend on the delay between a valid address and the time the memory devices produce the corresponding data value. This would sometimes result in periods of wait cycles where nothing was happening. Because of this, memory was considered to be "asynchronous".

However, Synchronous Dynamic Random Access Memory (SDRAM) eliminates this difference between memory speed and processor speed because SDRAM has a clock synchronized with the computer's central processing clock. Thus, SDRAM uses only the time required to read/write data which increases data transfer rates by eliminating non-productive periods of waiting. The clock coordinates with the processor and the memory so that data can be delivered continuously to the processor. The timing coordination between memory, the processor, and other support chips permits more efficient memory access and eliminates wait states. This results in memory access speeds of up to 20% faster than EDO.

Synchronous Graphics Random Access Memory (SGRAM)

Synchronous Graphics Random Access Memory (SGRAM) functions similarly to SDRAM except that it has added graphics support. Graphics support is provided by adding block write and mask write functionality.

Block write is used for doing block transfers, such as tiling. In tiling, the display screen is broken down into tiles that are manipulated by the graphics engine. With the block write function in the graphics memory, graphics engine overhead is reduced, freeing the engine to perform other tasks and boosting performance. Mask write aids system performance in areas such as color management of the screen. It simplifies changing selected bits in a block of data.