This document describes the hardware and software compatibility issues when designing a test environment for a 3-volt 'C548, but are temporarily using a 3-volt 'C542 device. There are a few simple things to consider before starting, such as:

1.) Pin compatibility -connection to peripheral devices.

2.) Clock Modes -PLL functionality.

3.) Memory Maps -differences in location of internal memory blocks.

4.) Instruction Set -Instructions supporting extended addressing.

Pin Compatibility

The 'C542 and 'C548 devices are packaged in a 144-pin TQFP and are footprint compatible. This means the peripheral and interface pinout of the 'C542 is upward compatible with the 'C548. However, the 'C548 offers a peripheral mix which can be thought of as a super-set of the 'C542 and therefore requires 13 additional pins. The physical location of these 13 extra pins on the 'C548 correspond to either No Connects (NC) or supply pins (Vdd/Vss) on the 'C542 device. The 'C548 uses these 'non-mutual' pins for either extended addressing pins or Buffered Serial Port (BSP) pins. Figure 1 shows the physical location of non-mutual pins on the 'C542.

Fig. 1 Differences in 'C542/C548 pinout (3-volt devices only)

As Fig 1 illustrates, eight of the 13 pins are NC and the remaining 5 are supply pins (either Vdd or Vss). The eight NC pins are don't care conditions (on the 'C542) due to no physical connection to the silicon die. The remaining 5 pins defined as either Vdd or Vss are used as extra supply pins, but are not required on the 3v devices. The decrease in supply pins is due to the high noise immunity of the 'C54x 3-volt process technology. When designing with 3-volt devices, these 5 pins can be left unconnected. The figure below lists the 13 pins and how they should be connected to support 'C542/'C548 compatibility.

* Indicates connection to supply not required on the 3V TMS320C542.

x Don't care.

Your test environment may include sockets for all of the necessary external logic, peripherals, devices, etc to support the 'C548 environment, but must remain unpopulated if they connect to a 'C542 supply pin. Only after the DSP socket is replaced with the 'C548 can the external peripheral sockets be populated. In other words, don't accidentally connect a device which strobes a VDD or GND signal of the 'C542!

The CNT pin is the 3v/5v configuration pin found on 3-volt 'C542 devices. This pin should always be left unconnected on the 'C548. This pin is reserved (TEST1) on the 'C548.

Clock Modes

The 'C542 and 'C548 devices both have 3 external CLKMD pins which configure the DSP internal clock frequency. The CLKMD[1,2,3] pins on the 'C548 offer different internal clock configurations than that of the 'C542. Both devices offer clock options via hardware configurations, but the 'C548 provides software programmability of it's PLL. As a result, the 'C548 has a much more flexible PLL with 31 different possible configurations. Only the four cases where CLMD3=1 provides compatibility between the 'C548 and 'C542 PLLs. Therefore, the only 'C542 hardware configuration compatible with the 'C548 is either Divide-by-two, stop mode or PLLx1 options. Please remember this document is only to clarify differences between the 'C548 and 'C542.....you can always change the hardware configuration after migrating to the 'C548.

Memory Maps

The internal memory configuration of the 'C548 has slight differences to the 'C542 memory map. The 'C542 has 10KWords of on-chip Dual-Access RAM (DARAM), whereas the 'C548 only has 8KWords of DARAM and 24KWords of Single-Access RAM (SARAM). Therefore when developing application code on the 'C542 DARAM, be aware of the differences in DARAM of the 'C548. The last 2KWord DARAM block is only SARAM on the 'C548. Performance degradation may occur in this particular 'C548 memory block if instructions with dual operands require DARAM.

Instruction Set

Due to the fact the 'C548 supports extended addressing, there were a few instructions added to the instruction set. For example, the normal 'C542 BRANCH (B) instruction performs a PC relative jump within a 64K address range. The 'C548 has included FAR BRANCHes (FB) which use the PC extension register (XPC). The XPC is a read-only memory-mapped register at location 0x1E. The following 6 instructions have been added to the 'C548 instruction set to support extended addressing:

FB[D] -Far Branch

FCALL[D] -Far Call

FRET[D] -Far Return

FBACC[D] -Far branch to location specified by accumulator A or B.

FCALA[D] -Far call to location specified by accumulator A or B.

FRETE[D] -Far return with interrupt enable.

A hardware RESET will initialize the XPC to 0x0000. The 'RESET'instruction does not affect the XPC contents.

In the 'C542 there are two instruction which perform program and data movement called READA and WRITA. The 'C542 versions of these instructions use the lower 16-bits [A15:A0] as a program memory address to move data/program to/from another memory space. However, with the 'C548 the instructions use the lower 23-bits [A22:A0] to perform the same data/program moves. So, after performing a data move with READA or WRITA, a simple clear of the lower 16-bits of the accumulator will not suffice. Be sure to clear the additional 7-bits [A22:A16].

Other instructions which use program addressing, such as MVPD, MVDP, MACD, MACP and FIRS will work within the current XPC page only. Block repeat instructions RPTB[D] must have block_start and block_end addresses in the same XPC page.

On-Chip Bootloader

The on-chip bootloaders of the 'C548 and 'C542 have several differences. The DSP performs consecutive reads from an external device which can be a Host on the HPI, EPROM, parallel I/O or serial port. The data which is read by the DSP must be in a particular format called a boot table. As with any 'C54x device , the boot table contains information on the destination address, section size, data format and other information. The 'C548 bootloader requires a different boot table format to support the extra functionality of the serial ports, and the extended address range. In fact, there are several registers which can be initialized in order to maximize the bootloader efficiency. For example, the 'C548 boot table includes information to re-program the Software Wait State generator and Bank Switch register for EPROM bootloads. If the serial ports are being used for bootloading, the same boot table locations act as register values for initialization of the serial port configuration registers. As a result, the bootloader supports full-function TDM and BSP bootloading. Normally, as with the 'C542 bootloader, registers are not reprogrammable and forces the serial ports into the Standard Mode of operation. The 'C548 HPI and I/O (using XF and BIO) bootloading has the same functionality as the 'C542.