Question : During a JTAG program download the   F240 full compare PWM outputs (PWM1-6) are not HIZ, even if /PDPINT = GND,   but toggle between high/low for a short period of time. This was observed with   older silicon revision 1.1.  Of course all PWM related registers are zero (after Reset) or PDPINT unmasked  and the PWM related registers are not modified by the program downloaded. 

Answer : In EV-Lite, there is one single output enable signal which serves for all the PWM outputs. So, before going offchip from the IO buffer, the enable signal takes care whether the PWM signals needs to be tristated. The logic which generates the enable signal is qualified by the PDPINTn interrupt (only when unmasked). So, PDPINTn active low (unmasked) will always lead to a HiZ on the PWM outputs.

About JTAG program download, I have  to say. There is a bit in the EV control register which when "0" means the PWM outputs are HiZ. At reset, this bit is "0". So, unless the user specifically writes a "1" on it, the PWM outputs will remain HiZ. So, only if the user tries to do a JTAG program download without a valid reset immediately preceding it, this problem should not arise. In case the user has to do a JTAG operation without a reset, then just before the JTAG operation, this particular bit in the control register needs to be disabled.