TMS320C203 / TMS320LC203 Silicon Errata

The following is a list of known problem on the TMS320C203/TMS320LC203 device.

I. Memory Interface

II. TRST Pin

III. DX Pin

IV. Memory range for Boot ROM

I. Memory Interface

Under certain conditions, the TMS320C203 and TMS320LC203 exhibit signal transitions on memory interface pins which are not consistent with the timing diagrams of the device datasheet. The following is a summary of these transitions and the conditions under which they occur:

The read/write (R/W), and memory strobe (STRB) pins pulse low during accesses to the on-chip I/O mapped registers. Though these signals are blocked while accessing internal I/O peripheral registers, signal transitions are seen at the beginning of the OUT and IN cycles.

1. The R/W pin exhibits a pulse of approximately 5ns during a write access (OUT) to any of the on-chip I/O mapped registers.
   
2. The STRB pin exhibits a pulse of approximately 3ns during a read access (IN) to any of the on-chip I/O mapped registers, while executing IN instruction from internal memory. For example, executing IN instruction using the repeat (RPT) instruction and executing IN instruction from B0 RAM.
   
3. The program select (PS) pin exhibits a low pulse during each transfer of the boot load operation. The PS pin pulses low for approximately 3ns after each read from global data space.

II. TRST Pin

The JTAG test reset pin (TRST), device pin 79, does not include an on-chip pull-down resistor. When this pin is not driven, an external pull-down resistor should be used. If the TRST pin is left unconnected without a pull-down resistor, then the TMS320C203 and TMS320LC203 could enter emulation mode. If the pin is held in the low state, then the device will remain in functional mode.

A 10Kohm resistor is sufficient, and should not exceed the drive current limits of emulation hardware.

During the boot load process, the last 256 words of global data space, addresses ff00h to ffffh, are not accessible to the CPU. Therefore, the TMS320C203 and TMS320LC203 has a maximum boot ROM range of 32K-256, or 32512 locations.