Question: C209 reset timing. Customer used the same
reset circuit as applied on C25 before like:

 
(1)   (  Low    -     High  ) sequence
                  ______________
  RS  ___________/
 
 
This timing DID work with C25 but NOT with C209 some times
even though both of C25 and C20x data sheet shows as:
 
(2) ( High   -   Low  -   High ) sequence
      _____             __________
  RS       \___________/           (C20x actually work only
      |    |                          with this timing.)
      |....| ? nsec
 
However, the first High signal period is not shown in
the user"s guide or data sheet, and most of power-on reset
ICs have (1) timing only. Also, there is no description
mentioned about High - Low - High reset sequence.
 
Answer: The waveform that you describe as 
#1 should work for resetting the "C209 at power-up. 
However, the duration of the low pulse is critical: 
The C209 requires that the reset pin (/RS) be held 
low for at least 6 CLKOUT1 cycles after the clock 
circuit is stable. If the on-chip PLL is being 
used, the duration of the reset pulse required 
will be much longer than that required by the 
"C25. Even if the PLL is bypassed (/2 mode), the 
start-up time of the oscillator used on the "C209 
based design may not be the same as that used on their 'C25 board.