Question: Needing a good staring point on Interfacing with the C32

Answer:
We reprinted an Application Note :
'EDRAM Memory Controller for the TMS320C31 DSP'

The only major change is that will be required is that the timing of the
/READY pin on the C32 is the same as the C4x, and not the C30/C31.  This is
a good feature of the C32 since it gives an additional H/2 cycle for
external decode logic.

This should be a good starting point for any type of DRAM, but if you go to
their web page you will also find application notes for connecting to other
TI DSP's, including the C4x. 

Some Other resources are at:
http://www.edram.com

The DRAM controllers job is to detect changes in the upper address bits, and
if detected insert a WS while a RAS/CAS is performed.  Additionally, if the
DRAM does not have internal refresh, a timer and counter would provide
refresh by cycling through all pages of the DRAM