TMS320C40 SILICON ERRATA
	   Rev 5.x Silicon  (Document Revision 1.0)
	   Last Modified:06/11/96

The following problems exist in TMS320C40 revision 5.X silicon or any 
lower revision (all speeds included unless specifically noted) known by 
TI as of the date given above.  Each problem is described and an appropriate 
work around is presented.  In addition, the revision in which the problem was
or is scheduled to be fixed is also shown.

TI creates a new document revision when a new silicon bug is discovered.  
However, TI does NOT update previously edited files.  For example, if you 
have silicon rev 2.1, you should review the last document revision for 2.x 
silicon AND the latest document revisions for newer silicon (i.e. 3.x, 4.x 
... document revisions) because unless specified, older silicon revisions 
have the problems that have been discovered in newer silicon.

New in this document:  Problem 5.0.1 

Bug listing:             Fixed                  Silicon rev. that fixed it
                                                (or will be)(Note 1)
                                                
                                                                        
PROBLEM 5.0.1   
Writes to DMA register
speed-path         	  no	                  5.2 (Note 2)

Note 1:  The Silicon bug is present in any device with a silicon revision
lower than this silicon version.  It will not be present in any silicon revision 
number greater than or equal to this silicon revision.

Note 2:  Any C4x 60Mhz device with a date code later than 9620 will not have
this problem

============================================================================
PROBLEM 5.0.1. Writes to DMA register speed-path (clock speed >50Mhz)

A DMA register may become corrupted due to an internal race condition during a 
DMA or CPU write to another register of the same DMA channel.  Writes to DMA
registers are done through the peripheral bus and are typically used during CPU
initialization of the DMA or during DMA autoinitialization. For the problem to occur,
all of the following conditions must be met:

1. The last access to the peripheral bus must be a write (if the peripheral
   bus has never been accessed, the failure will not occur).
2. The DMA register address being written must be different from the peripheral 
   address used during the last access to the peripheral bus.
3. In the previous cycle, an access to an address bus other than the peripheral 
   bus must occur.

An example of C4x code which meets these conditions is shown below:

DMA2 write to 0x100062 (comm port 2 output FIFO)
DMA5 write to Local Bus
DMA0 write to 0x1000a4 (DMA0 Destination address register)

In this example, a possible peripheral address decode glitch may cause the 
DMA0 write to 0x1000a4 to corrupt the 0x1000a6 address location  (DMA0 link pointer)
with the last value on the peripheral data bus (i.e. DMA2 write value).  If DMA0 is 
autoinitializing, the corruption of the link-pointer could cause further corruption
of other DMA registers.

This failure is aggravated at high clock speeds (>50Mhz) and high temperature. 
The failure is not present on TMS320C4x devices running at 50Mhz or slower.

                   WORK AROUNDS FOR CPU WRITES TO DMA REGISTERS
            
* WORK AROUND 1 (for systems with DMA synchronized peripheral bus accesses)

Stop all DMA peripheral bus activity before writing to the DMA register. An easy 
way to achieve this in systems in which all DMA accesses to the peripheral bus are 
synchronized is by setting the corresponding DMA DIE register bits to 0.

Example: Initialization of DMA0 control register

-original code:  
  sti r0,*ar0             ; ar0 = 0x1000a0

-replacement code:
  ldi   0,die             ; stop any DMA activity to the peripheral bus that is synchronized
  ldi  *ar0,r1            ; dummy read to set the previous peripheral bus address 
                            to the same DMA reg. address
|| sti  r0,*ar0           ; safe write to a DMA register
                     

* WORK AROUND 2 (for systems in which the CPU has higher priority than the DMA)

Example:  Initialization of DMA0 control register
-original code: 
   sti r0,*ar0            ; ar0 = 0x1000a0

-replacement code:
        ldi  *ar0,r1      ; dummy read to set the previous peripheral bus address 
                            to the same DMA reg. address
     || sti  r0,*ar0      ; safe write to a DMA register

If the CPU has higher priority than the DMA, a DMA will not access the peripheral bus 
in between the read (LDI) and write (STI) phases of the pipeline.


                                WORK AROUND FOR DMA WRITES TO DMA REGISTERS

WORK AROUND 3: DMA writes to DMA registers are typically done during autoinitialization.
Use the CPU (with work arounds 1 and 2 above) to initialize the DMA instead of using 
DMA autoinitialization. 

The following code presents an example:

  dma autoinit code
      LDI      @DMA,AR0	       ;  Load Control Register Pointer in AR0
      LDI      @DMA0CTL,R0     ;  Load DMA0 Control word in R0
      STI      R0,*+AR0(0)     ;  Init DMA 0 control
      LDI      @DMA0LNK,R0     ;  Load Link Pointer in R0
      STI      R0,*+AR0(6)     ;  Init DMA 0 Link Pointer
      LDI      @DMASTART,R0    ;  Load Start word in R0
      LDI      *+AR0(0),R1     ;  Load current DMA 0 Control Register in R1
      OR       R0,R1	       ;  Set start bits
      STI      R1,*+AR0(0)     ;  Store back to DMA Control Register

; cpu init code
      STI      DIE,@DIEMASK    ;  preserve DIE value
      LDI      0,DIE           ;  assuming work around 1
      LDI      @DMA,AR0        ;  Load Control Register Pointer in AR0
      LDI      @DMA0LNK,ar1    ;  Load autoinit table pointer in ar1
      LDI      *+AR1(1),R0     ;  init src address register
      LDI      *+AR0(1),R1
  ||  STI      R0,*+AR0(1)
      LDI      *+AR1(2),R0     ;  init src index register
      LDI      *+AR0(2),R1
  ||  STI      R0,*+AR0(2)
      LDI      *+ar1(3),R0     ;  init counter register
      LDI      *+AR0(3),R1
  ||  STI      R0,*+AR0(3)
      LDI      *+AR1(4),R0     ;  init dst address register
      LDI      *+AR0(4),R1
  ||  STI      R0,*+AR0(4)
      LDI      *+AR1(5),R0     ;  init dst index register
      LDI      *+AR0(5),R1
  ||  STI      R0,*+AR0(5)
      LDI      *+ar1(6),R0     ;  init link pointer register 
      LDI      *+AR0(6),R1
  ||  STI      R0,*+AR0(6)
      LDI      *AR1,R0	       ; init control register
      LDI      *AR0,R1
  ||  STI      R0,*AR0
      LDI      @DIEVAL,DIE


In the event of a second- or higher level autoinitialization, you can 
implement equivalent code inside an interrupt service routine that gets 
executed when a DMA block transfer completes (set the TCC bit or AUX TCC 
bits  to 1).