RMP
                   TMS320C44 SILICON ERRATA
                   Rev 1.x Silicon  (Document Revision 1.0)
                   Last Modified:01/23/95

 The following problems exist in the 320C44 rev.1x silicon(all speeds
 included) known by TI as of the date given above. Each problem is described and
 an appropriate work around is presented.  In addition, the revision in which
 the problem is fixed or will be fixed is included.

 TI creates a new document revision when a new silicon bug is discovered.
 However, TI will NOT update previously edited files. For example, if you have
 silicon rev 2.2, you should take a look at the last document revision for 2.x
 silicon AND to the latest document revisions for newer silicon (i.e. 3.x, 4.x
 ... document revisions) because unless specifically specified, old silicon has
 the bugs that have been discovered in newer silicon.

New in this document:  Problem 3.0.10
--------------------   Problem 3.0.11

Bug listing:                                            Fixed    Silicon.rev
-----------                                                      that fixed it
                                                                 (or will be)
                                                                 (Note 1)

PROBLEM 3.0.10 BK register ready pipeline conflict      no        1.1
PROBLEM 3.0.11 Cache logic                              no        1.1

Note 1: Silicon bug  present in any device with silicon revision lower than
        this silicon version. It will not be present in any silicon revision
        number greater than or equal to this silicon revision.

============================================================================
PROBLEM 3.0.10 BK register ready pipeline conflict

If the BK register is loaded  and one of the next 2 instructions uses
circular addressing that generates an address outside the block size
boundary, the wrong circular address may be generated.

The problem  is present only when the instruction using circular addressing
is a 3-operand or a parallel instruction. Following is an example illustrating
the problem.

      ldi 16,bk
      ldi 15,rc
      rptb again
      ldi 8,bk
again mpyf *ar3++%,*ar2++,r0    ; bug
 ||   addf r0,r2

When the problem occurs, the circular address is generated based on the previous
value of the BK register (BK=16) instead of with the new value (BK=8).
This results in a wrong circular addressing being generated.

WORKAROUNDS:
There are several workarounds for this problem:
1) add 2 NOPS after the loading of the BK register. This solution always
   works.

      ldi 16,bk
      ldi 15,rc
      rptb again
      ldi 8,bk
      nop
      nop
again mpyf *ar3++%,*ar2++,r0    ; no bug
 ||   addf r0,r2

2) In some cases the problem is limited to auxiliar registers AR0 to AR5.
When AR6 or AR7 is used for circular addressing generation the problem
doesn't exist. For example, in the example above, if AR3 is replaced by AR6 or
AR7, the problem dissapears.


3) For some instructions, reversing the order of the operand will solve the
   problem. An example is shown below:

      ldi 16,bk
      ldi 15,rc
      rptb again
      ldi 8,bk
again mpyf *ar2++,*ar3++%,r0    ; no bug
 ||   addf r0,r2

============================================================================
PROBLEM 3.0.11  Cache logic

In a very special condition, the C4x will execute an incorrect opcode
due to a bug in the cache logic.
 
For this cache problem to occur, all the following conditions should be met:
 
     1. Cache is enabled.
     2. Program is being fetch from external memory and shared memory scheme
        is used with DE_ and AE_ signals
     3. An interrupt occurs during the fetch phase of an instruction.
     4. The following sequence should occur after the interrupt is recognized:
        RDY_ goes high, address and data buses get tristated  and
        the data bus changes within 2 cycles after RDY_ goes high.


This causes the wrong instruction opcode to be stored in the cache.
Therefore upon returning from the interrupt  service routine, the correct
instruction is never executed.


WORK AROUND:
There are 2 workarounds for this problem:

1) Clear the cache inside the interrupt service routine.  An example is shown
  below:
 
Example 1:

ISR:
          PUSH       r10        ; Save the register value  (could be any reg)
          LDHI       1, r10
          OR         r10,st     ; CC=1
            :         :
            :         :
            :         :
            :         :
          POP        r10        ; Recover the register value
          RETI
 
2) After taking RDY_ high, wait 2 cycles to tristate the address and data
   buses