TI Home 
Search Feedback 
Semiconductor Home
A new generation of DSPs from Texas Instruments brings the power of DSP processing to designers of high-performance, cost-sensitive, emerging applications.
The TMS320C2xx generation combines 40 MIPS performance with ultra-low cost for the most optimal balance of price and performance of any DSP in the industry. In many cases, this allows designers of cost-sensitive applications like set-top boxes, feature phones, power-line monitors, solid-state relays, hard-disk drives, CD ROMs and modems to implement powerful DSP solutions for the first time.
"Starting as low as 12 cents per MIPS, the 'C2xx generation redefines the industry standard for price and performance in a fixed-point DSP," said Mark Mattson, TI fixed-point DSP marketing manager. "These devices enable emerging applications that otherwise might not have used DSP. The result is a much more powerful solution that enables more functionality for cost-sensitive applications."
'C2xx generation devices are the first discrete, off-the-shelf solutions designed around TI's T320C2xLP DSP core. The 'C2xLP core incorporates a static design and is manufactured in a sub-micron, triple-level metal, full-complementary CMOS process for high-performance, low-power operation. Features of the core include a 25ns instruction cycle time in 5-V mode and a 50ns instruction cycle in 3-V mode. The 'C2xLP core also features 544 x 16 words of internal dual-access RAM and 224K words of total address space.
Low power operation is optimized with the 'C2xx generation. In typical applications, the 'C2xx DSPs consume only 1.9 mA per MIPS at 5V and 1.1mA per MIPS at 3V. The 'C2xLP core also has a built-in power-down mode which drops power dissipation even further. Additional optimizing core features include /2 input clock option and five phase-locked loop (PLL) options (x1, x1.5, x2, x3 and x4) that allow the use of a slower clock. This lowers system power and noise external to the device.
The first two offerings in the 'C2xx generation are the TMS320C203 and the TMS320C209. Building on the 'C2xLP core, both devices add optimizing peripheral and memory configurations. In addition, both are source code-compatible with TMS320C1x and TMS320C2x fixed-point DSPs and upward compatible with TMS320C5x devices.
The 'C203 incorporates a 16-bit timer, a software wait-state generator, a synchronous serial port with a four-word deep buffer and an on-board universal asynchronous receiver/transmitter. (See "Three UARTs offer deep buffer and PnP") The 'C209 integrates the 'C2xLP core, a 16-bit timer, 4K X 16 words of on-chip RAM and 4K x 16 words of on-chip ROM for applications that can take advantage of the larger memory depths.
Space-constrained applications further benefit from 'C2xx generation packaging. The 'C209 is available in a 100-pin thin quad flatpack (TQFP) and the 'C209 is available in an 80-pin TQFP.
The 'C209 is currently available in an 80-pin TQFP package at 40 MHz (20 MIPS) and 57 MHz (28.5 MIPS) from TI and through distribution. Suggested high-volume pricing for the 40 MHz 'C209 is $9.50 each for 100,000-unit quantities and $9 each for 250,000-unit quantities.
The 'C203 is expected to sample and to be available through TI authorized distributors in the fourth quarter of 1995 at 40 MHz, 57 MHz and 80 MHz in a 100-pin TQFP package. Estimated high-volume production pricing for the 40-MHz (20 MIPS) 'C203 is targeted for $4.75 each for 100,000-unit quantities and $4.50 each for 250,000-unit quantities. Estimated high-volume production pricing for the 80-MHz (40 MIPS) 'C203 is targeted for $5.26 each in 100,000-unit quantities and $4.95 each for 250,000-unit quantities.
May 1995, vol. 12, no. 4