New DSP optimized for embedded applications

New DSP optimized for embedded applications

Texas Instruments expands its range of DSP solutions for embedded data and telecommunications applications with the announcement of a new peripheral-rich digital signal processor (DSP).

The new device, TI's TMS320C57S, is optimized for embedded applications such as mobile radios, navigational communications systems, cellular base stations and networking equipment including telephony switches, routers, wireless local loop infrastructure systems, and links to ATM, Ethernet and T1 lines.

The 'C57S integrates a high-performance 'C5x-series DSP CPU with 7K words of on-chip RAM, a zero-overhead buffered serial port (BSP) and a glueless host-port interface (HPI). The new device facilitates the large amount of data I/O required for communications applications while eliminating the I/O tasks placed on the DSP CPU.

Intelligent I/O peripherals

"While the 'C57S can operate at up to 40 MIPS, the power of this performance is in the capabilities of the on-chip intelligent peripherals," said Jim Larimer, TI fixed-point DSP applications manager.

With a dedicated on-chip memory bus, the full-duplex, 40 Mbits/second BSP improves system performance by eliminating the need for the DSP CPU to service real-time data-frame interrupts from system I/O peripherals such as CODECs or A/D converters. Similarly, the independent 8-bit HPI requires no DSP CPU loading, providing a direct interface between the 'C57S and standard host microprocessors or other DSPs. Both peripherals are fully functional even when the 'C57S is in idle or reset mode, reducing system power consumption.

The combined processing and peripheral features of the 'C57S make it suitable as a data I/O engine for any DSP application that requires high-speed serial transmission, host-processor communication, large amounts of on-chip code and/or data, plus low power and high-performance.

Various boot-loader modes allow the 'C57S to boot from an 8-bit EPROM, the chip's standard serial port or the HPI for a high degree of system-design flexibility.

Low-cost alternative

The new device is a lower-cost version of TI's TMS320LC57. It has four distinct differences from the previous device:

Lower cost
Both 5-V and 3.3-V operation
On-chip bootloader instead of large on-chip ROM
.5mm lead pitch packaging

Price and availability

Available in a 144-pin TQFP, the 'C57S will sample in 3Q95 and ship at full production levels late in the fourth quarter.


TMS320C57S       40 MHz        $24.25

                 57 MHz        $26.50

                 80 MHz        $30.60

This listing provides budgetary estimates per unit in 10K quantity.

May 1995, vol. 12, no. 4

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