
By Wayne Daniel, senior product engineer
The following excerpt, written by Wayne Daniel, senior product engineer at Texas Instruments, is from the full text, which appears in EETime's ITC issue and on TI's Home Page on the World Wide Web (http://www.ti.com).
The growth of graphics-oriented operating systems and applications has created a data bottleneck between the processor and peripherals. To address this problem, the Peripheral Component Interconnect (PCI) local bus was developed to handle graphics and other high bandwidth needs (such as disk and LAN I/O) of high-performance computers.
The PCI local bus developers recognized the importance of test and reserved five signal pins for the IEEE 1149.1 test bus. The PCI local bus specification allows the IEEE 1149.1 to be connected in a system in three ways:
To demonstrate and validate the use of IEEE 1149.1 in a common multi-drop multi-card system, TI used a PC with an integrated PCI local bus as a proof-of-concept system. The PC system consists of an off-the-shelf x86-based PC motherboard with three PCI bus slots and three PCI add-in cards. The IEEE 1149.1 pins, initially no-connects on this motherboard, were connected in a multi-drop (bused) fashion.
Three PCI add-in cards, each containing one or more IEEE 1149.1 integrated circuits, were used in the proof-of-concept system. All three PCI add-in cards were modified to include a TI SN74ABT8996 Addressable Scan Port (ASP) IC to connect the backplane IEEE 1149.1 bus to the card's internal IEEE 1149.1 bus.
The combination of a PCI local bus, multi-drop IEEE 1149.1 signals on the backplane and PCI add-in cards with ASPs demonstrates a flexible, hierarchical embedded test solution.
TI will demonstrate this proof-of-concept system at ITC.
ThunderLAN is a trademark of Texas Instruments Incorporated.
October 1995, vol. 12, no. 7
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