July 1996, vol.13, no. 5 DSP news Wireless news Networking news Logic news TI news

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New HyperSAR+ chipset connects LANs to ATM networks Complete chipset with full ATM Available Bit Rate (ABR) traffic management solution TNETA1575 Segmentation and Reassembly (SAR) device Pin-compatible with TNETA1570 Fully defined scheduler interface Extended receive channel and VPI/VCI support Supports up to 2,048 simultaneous segmentation and reassembly operations TNETA1585 Traffic Management Solution Fully defined interface to TNETA1575 SAR Provides scheduling for up to 2,048 simultaneous ABR connections Supports applicable ATM Forum and ITU standards TI has announced sampling of a new chipset enabling a flexible, cost-effective available bit rate (ABR) solution. It provides a high-performance connection between Ethernet and token ring local area networks (LANs) and asynchronous transfer mode (ATM) networks. Dubbed HyperSAR+™, the chipset incorporates a high-performance segmentation and reassembly (SAR) -- named TNETA1575 -- with a traffic management scheduler --named TNETA1585. The chipset provides existing HyperSAR (TNETA1570) users with a pinout compatible upgrade to traffic management from their current designs. The HyperSAR+ chipset is designed to simplify the original equipment manufacturer's product development cycle by offering a two-chip solution and all the necessary software to implement ABR traffic management. The chipset gives the flexibility to add ABR functionality as needed. The chipset can be combined with the TNETA1500 ATM physical layer interface device for a complete 155 Mbps ATM uplink capability. The HyperSAR+ is ideal for applications that require simultaneous, efficient transport of bursty data along with constant bit rate (CBR) video and audio. The device supports the full ATM address range (VPI/VCI values) required for virtual LANs. The fully defined scheduler interface on the SAR allows OEMs to offer a differentiated solution. In addition, the SAR eliminates the need for a large off-chip SRAM through intelligent, efficient algorithms for channel allocation. The HyperSAR+ traffic management scheduler enables an ABR implementation that supports up to 2,048 simultaneously active ABR channels, facilitating LAN emulation. The traffic management scheduler is a software downloadable device with a well-defined interface to the HyperSAR+. Housing the traffic management scheduler on a separate chip enables designers to track the ABR specification and incorporate modifications by downloading updated code to the scheduler, rather than changing hardware designs. The HyperSAR+ chipset conforms to the ATM Forum Traffic Management 4.0 specification and the ITU-T I-371 Recommendation (formally called the CCITT). Planned packaging for the HyperSAR+ Traffic Management chipset is a 240-pin plastic quad flat pack (PQFP) for the HyperSAR+ and a 176-pin thin plastic quad flat pack (TQFP) for the traffic management scheduler. HyperSAR+ samples and prototypes will be available to customers in August. The traffic management scheduler will be available 4Q96.

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