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September 1996, vol.13, no. 6
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New 16-Mbit synchronous DRAM offers lower cost and improved performance for PC graphics
TI has recently disclosed a new 32-bit wide 16-Mbit synchronous DRAM (SDRAM) that will improve performance while reducing costs by cutting chip count in mainstream PC graphics subsystems.
The high-density SDRAM device offers higher performance and lower replacement costs than either four 4-Mbit extended data output (EDO) memories or two 8-Mbit synchronous graphics RAM (SGRAM) devices.
"We expect 16-Mbit SDRAM memory to become the technology of choice for graphics subsystems because it provides an easy way for vendors to reduce the cost of their PC graphics boards and to simplify their designs," said Anthony Balistreri, manager of TI's Graphics Memory Development. "In the case of 4-Mbit EDO memories, four chips can be replaced with one 16-Mbit device and the performance will increase by approximately 20 percent. In comparison to 8-Mbit SGRAMs, 16-Mbit SDRAMs will lower cost by reducing the number of components and, in addition, SGRAMs are more expensive because they have integrated circuitry for features that aren't needed by mainstream PCs. Since 16-Mbit SDRAMs are drop-in replacements for 8-Mbit SGRAMs, a major re-design effort is not needed either." The 16-Mbit devices are synchronized to the system's clock to simplify design and enhance their use with high-speed microprocessors and controllers. For example, with a system clock speed of 125 MHz, two 16-Mbit SDRAMs can provide graphics data at a rate of one gigabyte per second (GB/s) over the typical PC's 64-bit graphics bus. Because of their high bandwidth, the 16-Mbit SDRAMs are appropriate for other applications, such as set-top boxes, palm-top computers, personal digital assistants (PDAs), inexpensive network computers, video game consoles and video conferencing systems. Designed for graphics throughputThe devices are organized 256K words by 32 bits by two banks (256K x 32 x 2) to provide interleaved access. Interleaving operations between two banks of memory locations allows one bank to be accessed while a memory address in the second bank is being activated. When the access in the first bank has been completed, data from the second bank can be provided without interruption for a constant flow of data.TI will supply 16-Mbit SDRAM in JEDEC-standard 100-pin QFP packages. The 3.3-V devices will be fabricated using TI's EPIC™(enhanced performance implanted CMOS) process for high performance, reliability and low power. Samples will be available during the first quarter of 1997. Volume production is scheduled for the fourth quarter of 1997.
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