1394 Applications Archive
Q: How may I correctly initiate 1394 bus resets from SW?
A: To initiate a bus reset from SW for a 1394-1995 PHY layer,
the link layer will use the "PHY Chip Access" register to write
into PHY register "0001b" to change the state of the Initiate
Bus Reset (IBR) bit. The trick is, as suggested by 1394-1995
and required by 1394.A, this bit is in the same register as the
gap count and root hold-off bit (RHB). Therefore any time the
IBR bit is written to, the gap count and RHB are also written
to. The recommended SW sequence is to read the PHY register,
change, in memory only, the bits that need to be changed while
keeping the other bits the same, then writing this changed
value back into the PHY register to modify the register. The
only case a value other than 3F hex should be written into the
gap_count field during the initiation of a bus reset is the case
of a bus reset initiated by SW immediately after a PHY
configuration packet has been sent to set the gap counts of each
node. In this case the gap count written during the write to the
IBR bit should be the same as the gap count written by the
immediately previous PHY configuration packet. For all other
initiations of bus reset by writing the IBR bit, the gap counts
should be set to 3F. This is required since after every 2 bus
resets (unless a gap count register write is done in-between the
resets) all gap counts are reset to the default 3F. Writing 3F
ensures that all gap counts on all nodes on a bus are set to the
same value. The RHB should be written with the value it currently
holds to ensure no unexpected changes in bus topology.
To initiate a bus reset from SW for a 1394.A PHY layer, the same
procedure may be followed. However, 1394.A also defined an
Arbitrated Short Bus Reset which is initiated by writing a 1 to
the Initiate Short Bus Reset (ISBR) bit of PHY register 0101b.
Since the PHY gap count is in another PHY register (register 0001b)
this avoids any problem with overwriting gap counts or changing the
state of RHB during initiation of a bus reset. However, this
register contains PHY interrupts and 1394.A enhancement enable bits.
So SW must take care not to change a bit value it is not desired to
change, when initiating a bus reset. It is recommended that in a
1394.A system the ISBR bit be utilized for SW initiated bus resets.
